DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) filed on January 17, 2025 has been considered by the examiner.
Status of the Claims
Claims 3, 5, 8, 22, and 25-30 are cancelled. Claims 4, 6-7, 9-10, 12-15, and 23-24 are amended. Claims 1-2, 4, 6-7, 9-21, and 23-24 are present for examination.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9, 12-20, and 23-24 are rejected under 35 U.S.C. 103 as being unpatentable over Jia (US 2019/0103452 A1) in view of Lee (US 2022/0131111 A1).
Claim 1, Jia discloses a display substrate (base substrate 10 and patterned film layer 20 is a display substrate, hereinafter, display substrate 10/20, [0036], Figs. 1(a), 8, and 9), comprising a pixel driver circuit (patterned film layer 20 includes thin film transistor 21, further including the driving circuit of each pixel, hereinafter, pixel driver circuit 20, [0081], Figs. 1(a), 8 and 9) and a plurality of first electrodes (a plurality of first electrodes is resultant when each first electrode 50 is electrically in contact with each individual transistor 21, hereinafter, plurality of first electrodes 50, [0089], Figs. 1(a), 8, and 9) on the pixel driver circuit 20 (plurality of first electrodes 50 is on the pixel driver circuit 20, [0089], Figs. 1(a), 8, and 9), wherein
the pixel driver circuit 20 comprises a base 10 (pixel driver circuit 20 comprises a base substrate 10 which is a base, hereinafter, base 10), and a plurality of first signal wires 21 in a same layer (pixel driver circuit 20 comprises a base 10 and a plurality of first signal wires 21 within the planarization layer 30, which is a same layer, hereinafter, same layer 30, [0089], Figs. 1(a), 8, and 9) on the base 10 (pixel driver circuit 20 comprises a base 10 and a plurality of first signal wires 21 within the same layer 30 on the base 10, [0089], Figs. 1(a), 8, and 9);
the plurality of first signal wires 21 have the same extending direction (plurality of first signal wires 21 within pixel driver circuit 20 extend in a horizontal direction, [0099], Figs. 1(a), 8, and 9);
the first electrodes 50 and the first signal wires 21 are in different layers (first electrodes 50 and the first signal wires 21 are in different layers (i.e. under-lying the planarization layer 30 vs. above the planarization layer 30), [0099], Figs. 1(a), 8, and 9);
orthographic projections of the first signal wires 21 on the base 10 are partially overlapped with orthographic projections of the first electrodes 50 on the base 10 (orthographic projections of the first signal wires 21 on the base 10 are partially overlapped with orthographic projections of the first electrodes 50 on the base 10, [0099], Figs. 1(a), 8, and 9);
the first electrodes 50 each have a strip shape (first electrodes 50 each have a strip shape, as seen from a cross-sectional view, [0089], Figs. 1(a), 8, and 9), and the plurality of first electrodes 50 are arranged in an array along a length direction and a width direction of the strip shape (plurality of first electrodes 50 are arranged in an array along a length direction and a width direction of the strip shape, [0089], Figs. 1(a), 8, and 9);
the display substrate 10/20 further comprises an auxiliary leveling structure (planarization layer 30 further includes first planarization sub-layer 301 and second planarization sub-layer 302 and is an auxiliary leveling structure, hereinafter, auxiliary leveling structure 30, [0088], Figs. 1(a), 8, and 9) on a side of the first signal wires 21 away from the base 10 and a side of the first electrodes 50 close to the base 10 (auxiliary leveling structure 30 is on a side of the first signal wires 21 away from the base 10 and a side of the first electrodes 50 close to the base 10, [0088], Figs. 1(a), 8, and 9), and an orthographic projection of the auxiliary leveling structure 30 on the base 10 covers at least the orthographic projections of the first electrodes 50 on the base 10 (an orthographic projection of the auxiliary leveling structure 30 on the base 10 covers at least the orthographic projections of the first electrodes 50 on the base 10, [0089], Figs. 1(a), 8, and 9); and
the auxiliary leveling structure 30 enables a layer of the first electrodes 50 flat (auxiliary leveling structure 30 enables a layer of the first electrodes 50 flat, [0088], Figs. 1(a), 8, and 9).
Jia does not explicitly disclose the extending direction of the first signal wires forms acute angles greater than 0o and smaller than 90o with the length direction and the width direction of the strip, respectively.
However, Lee discloses the extending direction of the first signal wires (Lee, second sensing electrode IE2-1 – IE2-4 are individual first signal wires in a mesh shape, hereinafter, first signal wires IE2-1 – IE2-4, [0119], Figs. 8 and 9; Jia, first signal wires 21, [0099], Figs. 1(a), 8, and 9) forms acute angles greater than 0o and smaller than 90o with the length direction and the width direction of the strip, respectively (Lee, first signal wires IE2-1 – IE2-4 forms acute angles greater than 0o and smaller than 90o with the length direction (i.e. x-direction) and the width direction (i.e. y-direction) of the input sensing layer 40 which is the strip, hereinafter, strip 40, respectively, [0119], Figs. 8 and 9; Jia, first signal wires 21, [0099], Figs. 1(a), 8, and 9).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to vary, through routine experimentation, “the result effective variable of first signal wires forms acute angles greater than 0o and smaller than 90o with the length direction and the width direction of the strip (result effective at least insofar as first signal wires forms acute angles greater than 0o and smaller than 90o with the length direction and the width direction of the strip results in deterioration in sensing sensitivity is reduced or effectively prevented by reducing or effectively preventing a voltage drop in the detection signal (or the transmission signal (Lee, [0126])) in order to optimize the functionality of the device (In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), see MPEP §2144.05).
Further, the specification contains no disclosure of either the critical nature of the claimed first signal wires forms acute angles greater than 0o and smaller than 90o with the length direction and the width direction of the strip or any unexpected results arising therefrom and it has been held that where patentability is said to be based upon a particular chosen dimension or upon another variable recited in a claim, the Applicant must show that the chosen dimension is critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claim 2, Jia/Lee discloses the display substrate (Jia, display substrate 10/20, [0036], Figs. 1(a), 8, and 9; Lee, display apparatus 1 includes a display substrate, [0130], Figs. 8 and 9) according to claim 1.
Jia/Lee discloses wherein the auxiliary leveling structure (Lee, thin-film encapsulation layer 300 is an auxiliary leveling structure, hereinafter, auxiliary leveling structure 300, [0159], Figs. 8 and 9; Jia, auxiliary leveling structure 30, [0088], Figs. 1(a), 8, and 9) comprises a plurality of planarization layers (Lee, auxiliary leveling structure 300 further includes a plurality of planarization layers (i.e. first inorganic layer 310, organic layer 320, and second inorganic layer 330), hereinafter, plurality of planarization layers 310/320/330, [0159] and [0161], Figs. 8 and 9; Jia, auxiliary leveling structure 30 further includes a plurality of planarization layers (i.e. first planarization sub-layer 301 and second planarization sub-layer 302), hereinafter, plurality of planarization layers 301/302, [0088], Figs. 1(a), 8, and 9) having orthographic projections on the base covering an orthographic projection of the pixel driver circuit on the base (Lee, auxiliary leveling structure 300 having orthographic projections on the first base layer 101 which is a base, hereinafter, base 101 covering an orthographic projection of the pixel driver circuit PC (i.e. including a thin-film transistor TFT and a storage capacitor Cst, and each display element may include an organic light-emitting diode OLED) which is a pixel driver circuit, hereinafter, pixel driver circuit PC on the base 101, [0159] and [0161], Figs. 8 and 9; Jia, auxiliary leveling structure 30 having orthographic projections on the base 10 covering an orthographic projection of the pixel driver circuit 20 on the base 10, [0088], Figs. 1(a), 8, and 9);
the plurality of planarization layers are sequentially stacked on a side of the first signal wires away from the base (Lee, plurality of planarization layers 310/320/330 are sequentially stacked on a side of the pixel electrode 210 which is this first signal wire, hereinafter, first signal wires 210/440 away from the base 101, [0071] and [0161], Figs. 8 and 9; Jia, plurality of planarization layers 301/302, [0088], Figs. 1(a), 8, and 9), and a surface, close to the first electrodes, of one of the planarization layers closest to the first electrodes is planar (Lee, a surface, close to the first electrodes 440, of one of the planarization layers 310/320/330 closest to the first electrodes 440 is planar (i.e. planarization layer 330 is planar on both surfaces), [0159] and [0161], Figs. 8 and 9; Jia, a surface, close to the first electrodes 50, of one of the planarization layers planarization layers 302 closest to the first electrodes 50 is planar, [0088], Figs. 1(a), 8, and 9); and
each first electrode is a planar layer (Lee, each first electrode 440 is a planar layer, [0159] and [0161], Figs. 8 and 9; Jia, each first electrode 50 is a planar layer, [0088], Figs. 1(a), 8, and 9).
Claim 4, Jia/Lee discloses the display substrate (Jia, display substrate 10/20, [0036], Figs. 1(a), 8, and 9; Lee, display apparatus 1 includes a display substrate, [0130], Figs. 8 and 9) according to claim 2.
Jia/Lee discloses wherein the auxiliary leveling structure further comprises a dummy structure between any two adjacent planarization layers (Lee, auxiliary leveling structure 300 further comprises a dummy structure between any two adjacent planarization layers 310/320/330 in a horizontal direction (i.e. x-direction), [0159], Figs. 8 and 9; Jia, auxiliary leveling structure 30 further comprises a dummy structure between any two adjacent planarization layers 301/302, [0120], Figs. 1(a), 8, and 9) or in the same layer as the first signal wires (Lee, auxiliary leveling structure 300 further comprises a dummy structure in the same layer as the first signal wires 440, [0159], Figs. 8 and 9; Jia, auxiliary leveling structure 30 further comprises a dummy structure in the same layer as the first signal wires 21, [0120], Figs. 1(a), 8, and 9) and distributed at least in a region of an orthographic projection of a corresponding first electrode on the base (Lee, auxiliary leveling structure 300 further comprises a dummy structure distributed at least in a region of an orthographic projection of a corresponding first electrode 230 on the base 101, [0159], Figs. 8 and 9; Jia, auxiliary leveling structure 30 further comprises a dummy structure distributed at least in a region of an orthographic projection of a corresponding first electrode 50 on the base 10, [0120], Figs. 1(a), 8, and 9); and
an orthographic projection of the dummy structure on the base is not overlapped with the orthographic projections of the first signal wires on the base (Lee, an orthographic projection of the dummy structure on the base 101 is not overlapped with the orthographic projections of the first signal wires 440 on the base 101, [0159], Figs. 8 and 9; Jia, an orthographic projection of the dummy structure on the base 10 is not overlapped with the orthographic projections of the first signal wires 21 on the base 10, [0120], Figs. 1(a), 8, and 9), and forms a complementary pattern with the orthographic projections of the first signal wires on the base (Lee, an orthographic projection of the dummy structure on the base 101 forms a complementary pattern with the orthographic projections of the first signal wires 440 on the base 101, [0159], Figs. 8 and 9; Jia, an orthographic projection of the dummy structure on the base 10 forms a complementary pattern with the orthographic projections of the first signal wires 21 on the base 10, [0120], Figs. 1(a), 8, and 9).
Claim 6, Jia/Lee discloses the display substrate (Jia, display substrate 10/20, [0036], Figs. 1(a), 8, and 9; Lee, display apparatus 1 includes a display substrate, [0130], Figs. 8 and 9) according to claim 2.
Jia/Lee discloses wherein the auxiliary leveling structure further comprises a plurality of dummy structures in the same layer as the first signal wires (Lee, auxiliary leveling structure 300 further comprises a plurality of dummy structures in the same layer as the first signal wires 440, [0159], Figs. 8 and 9; Jia, auxiliary leveling structure 30 further comprises a plurality of dummy structures in the same layer as the first signal wires 21, [0120], Figs. 1(a), 8, and 9) or between any two adjacent planarization layers (Lee, auxiliary leveling structure 300 further comprises a plurality of dummy structure between any two adjacent planarization layers 310/320/330 in a horizontal direction (i.e. x-direction), [0159], Figs. 8 and 9; Jia, auxiliary leveling structure 30 further comprises a plurality of dummy structure between any two adjacent planarization layers 301/302, [0120], Figs. 1(a), 8, and 9) and distributed at least in a region of an orthographic projection of a corresponding first electrode on the base (Lee, auxiliary leveling structure 300 further comprises a plurality of dummy structures distributed at least in a region of an orthographic projection of a corresponding first electrode 440 on the base 101, [0159], Figs. 8 and 9; Jia, auxiliary leveling structure 30 further comprises a plurality of dummy structures distributed at least in a region of an orthographic projection of a corresponding first electrode 50 on the base 10, [0120], Figs. 1(a), 8, and 9); and
orthographic projections of the dummy structures on the base are not overlapped with the orthographic projections of the first signal wires on the base (Lee, orthographic projections of the dummy structures on the base 101 are not overlapped with the orthographic projections of the first signal wires 440 on the base 101, [0159], Figs. 8 and 9; Jia, orthographic projections of the dummy structures on the base 10 and orthographic projections of the first signal wires 21 on the base 10, [0120], Figs. 1(a), 8, and 9), and the orthographic projections of adjacent first signal wires on the base, the orthographic projections of each dummy structure and an adjacent first signal wire on the base, and the orthographic projections of adjacent dummy structures on the base, are equally spaced (Lee, the orthographic projections of adjacent first signal wires 440 on the base 101, the orthographic projections of each dummy structure and an adjacent first signal wire 440 on the base 101, and the orthographic projections of adjacent dummy structures on the base 101, are equally spaced, [0159], Figs. 8 and 9; Jia, the orthographic projections of adjacent first signal wires 21 on the base 10, the orthographic projections of each dummy structure and an adjacent first signal wire 21 on the base 10, and the orthographic projections of adjacent dummy structures on the base 10, are equally spaced, [0120], Figs. 1(a), 8, and 9).
Claim 7, Jia/Lee discloses the display substrate (Jia, display substrate 10/20, [0036], Figs. 1(a), 8, and 9; Lee, display apparatus 1 includes a display substrate, [0130], Figs. 8 and 9) according to claim 6.
Jia/Lee discloses wherein the plurality of first signal wires are parallel to each other (Lee, plurality of first signal wires 440 are parallel to each other, [0159], Figs. 8 and 9; Jia, plurality of first signal wires 21 are parallel to each other, [0120], Figs. 1(a), 8, and 9);
the orthographic projections of adjacent first signal wires on the base, the orthographic projections of each dummy structure and an adjacent first signal wire on the base, and the orthographic projections of adjacent dummy structures on the base, are spaced by a distance less than or equal to a minimum line width of the first signal wires (Lee, the orthographic projections of adjacent first signal wires 440 on the base 101, the orthographic projections of each dummy structure and an adjacent first signal wire 440 on the base 101, and the orthographic projections of adjacent dummy structures on the base 101, are spaced by a distance less than or equal to a minimum line width of the first signal wires 440, [0159], Figs. 8 and 9; Jia, the orthographic projections of adjacent first signal wires 21 on the base 10, the orthographic projections of each dummy structure and an adjacent first signal wire 21 on the base 10, and the orthographic projections of adjacent dummy structures on the base 10, are spaced by a distance less than or equal to a minimum line width of the first signal wires 21, [0120], Figs. 1(a), 8, and 9); and
a width of each dummy structure in an arrangement direction of the plurality of first signal wires is less than or equal to the minimum line width of the first signal wires (Lee, a width of each dummy structure in an arrangement direction of the plurality of first signal wires 440 is less than or equal to the minimum line width of the first signal wires 440, [0159], Figs. 8 and 9; Jia, a width of each dummy structure in an arrangement direction of the plurality of first signal wires 21 is less than or equal to the minimum line width of the first signal wires 21 [0120], Figs. 1(a), 8, and 9).
Claim 9, Jia/Lee discloses the display substrate (Jia, display substrate 10/20, [0036], Figs. 1(a), 8, and 9; Lee, display apparatus 1 includes a display substrate, [0130], Figs. 8 and 9) according to claim 1.
Jia/Lee discloses wherein the auxiliary leveling structure comprises a plurality of dummy structures and a plurality of planarization layers (Lee, auxiliary leveling structure 300 further comprises a plurality of dummy structures and a plurality of planarization layers 310/320/330, [0159], Figs. 8 and 9; Jia, auxiliary leveling structure 30 further comprises a plurality of dummy structures and a plurality of planarization layers 301/302, [0120], Figs. 1(a), 8, and 9), and orthographic projections of the plurality of planarization layers on the base cover an orthographic projection of the pixel driver circuit on the base (Lee, orthographic projections of the plurality of planarization layers 310/320/330 on the base 101 cover an orthographic projection of the pixel driver circuit PC on the base 101, [0159], Figs. 8 and 9; Jia, orthographic projections of the plurality of planarization layers 301/302 on the base 10 cover an orthographic projection of the pixel driver circuit 20 on the base 10, [0120], Figs. 1(a), 8, and 9);
the plurality of dummy structures are in the same layer as the first signal wires (Lee, auxiliary leveling structure 300 further comprises a plurality of dummy structures in the same layer as the first signal wires 440, [0159], Figs. 8 and 9; Jia, auxiliary leveling structure 30 further comprises a plurality of dummy structures in the same layer as the first signal wires 21, [0120], Figs. 1(a), 8, and 9) or between any two adjacent planarization layers (Lee, auxiliary leveling structure 300 further comprises a plurality of dummy structures between any two adjacent planarization layers 310/320/330 in a horizontal direction (i.e. x-direction), [0159], Figs. 8 and 9; Jia, auxiliary leveling structure 30 further comprises a plurality of dummy structures between any two adjacent planarization layers 301/302, [0120], Figs. 1(a), 8, and 9); and
the plurality of dummy structures are distributed at least in a region of an orthographic projection of a corresponding first electrode on the base (Lee, auxiliary leveling structure 300 further comprises a plurality of dummy structures distributed at least in a region of an orthographic projection of a corresponding first electrode 230 on the base 101, [0159], Figs. 8 and 9; Jia, auxiliary leveling structure 30 further comprises a plurality of dummy structures distributed at least in a region of an orthographic projection of a corresponding first electrode 50 on the base 10, [0120], Figs. 1(a), 8, and 9);
orthographic projections of the dummy structures on the base are not overlapped with the orthographic projections of the first signal wires on the base (Lee, orthographic projections of the dummy structures on the base 101 are not overlapped with the orthographic projections of the first signal wires 440 on the base 101, [0159], Figs. 8 and 9; Jia, orthographic projections of the dummy structures on the base 10 and orthographic projections of the first signal wires 21 on the base 10, [0120], Figs. 1(a), 8, and 9), and the orthographic projections of adjacent first signal wires on the base, the orthographic projections of each dummy structure and an adjacent first signal wire on the base, and the orthographic projections of adjacent dummy structures on the base, are equally spaced (Lee, the orthographic projections of adjacent first signal wires 440 on the base 101, the orthographic projections of each dummy structure and an adjacent first signal wire 440 on the base 101, and the orthographic projections of adjacent dummy structures on the base 101, are equally spaced, [0159], Figs. 8 and 9; Jia, the orthographic projections of adjacent first signal wires 21 on the base 10, the orthographic projections of each dummy structure and an adjacent first signal wire 21 on the base 10, and the orthographic projections of adjacent dummy structures on the base 10, are equally spaced, [0120], Figs. 1(a), 8, and 9); and
the plurality of planarization layers are sequentially stacked on a side of the first signal wires away from the base (Lee, plurality of planarization layers 310/320/330 are sequentially stacked on a side of the pixel electrode 210 which is this first signal wire, hereinafter, first signal wires 210 away from the base 101, [0071] and [0161], Figs. 8 and 9; Jia, plurality of planarization layers 301/302, [0088], Figs. 1(a), 8, and 9), and a surface, close to the first electrodes, of one of the planarization layers closest to the first electrodes is a uniformly concaved surface (Lee, a surface, close to the first electrodes 440, of one of the planarization layers 310/320/330 closest to the first electrodes 440 is a uniformly concaved surface, [0159] and [0161], Figs. 8, 9, and 14; Jia, a surface, close to the first electrodes 50, of one of the planarization layers planarization layers 301/302 closest to the first electrodes 50 is a uniformly concaved surface, [0088], Figs. 1(a), 8, and 9).
Claim 12, Jia/Lee discloses the display substrate (Jia, display substrate 10/20, [0036], Figs. 1(a), 8, and 9; Lee, display apparatus 1 includes a display substrate, [0130], Figs. 8 and 9) according to claim 2.
Jia/Lee discloses wherein one of the planarization layers closest to the first signal wires has a larger thickness than a thickness of the first signal wires (Lee, one of the planarization layers 320 closest to the first signal wires 210 has a larger thickness than a thickness of the first signal wires 210, [0071] and [0161], Figs. 8 and 9; Jia, plurality of planarization layers 301/302, [0088], Figs. 1(a), 8, and 9).
Claim 13, Jia/Lee discloses the display substrate (Jia, display substrate 10/20, [0036], Figs. 1(a), 8, and 9; Lee, display apparatus 1 includes a display substrate, [0130], Figs. 8 and 9) according to claim 6.
Jia/Lee discloses wherein the plurality of dummy structures are between any two adjacent planarization layers (Lee, auxiliary leveling structure 300 further comprises a plurality of dummy structure between any two adjacent planarization layers 310/320/330 in a horizontal direction (i.e. x-direction), [0159], Figs. 8 and 9; Jia, auxiliary leveling structure 30 further comprises a plurality of dummy structure between any two adjacent planarization layers 301/302, [0120], Figs. 1(a), 8, and 9), and each dummy structure has a thickness less than or equal to a thickness of the first signal wires (Lee, each dummy structure has a thickness less than or equal to a thickness of the first signal wires 440, [0159], Figs. 8 and 9; Jia, each dummy structure has a thickness less than or equal to a thickness of the first signal wires 21, [0120], Figs. 1(a), 8, and 9).
Claim 14, Jia/Lee discloses the display substrate (Jia, display substrate 10/20, [0036], Figs. 1(a), 8, and 9; Lee, display apparatus 1 includes a display substrate, [0130], Figs. 8 and 9) according to claim 6.
Jia/Lee discloses wherein the plurality of dummy structures are in the same layer as the first signal wires (Lee, auxiliary leveling structure 300 further comprises a plurality of dummy structures in the same layer as the first signal wires 440, [0159], Figs. 8 and 9; Jia, auxiliary leveling structure 30 further comprises a plurality of dummy structures in the same layer as the first signal wires 21, [0120], Figs. 1(a), 8, and 9), and each dummy structure has a thickness equal to a thickness of the first signal wires (Lee, each dummy structure has a thickness equal to a thickness of the first signal wires 440, [0159], Figs. 8 and 9; Jia, each dummy structure has a thickness equal to a thickness of the first signal wires 21, [0120], Figs. 1(a), 8, and 9).
Claim 15, Jia/Lee discloses the display substrate (Jia, display substrate 10/20, [0036], Figs. 1(a), 8, and 9; Lee, display apparatus 1 includes a display substrate, [0130], Figs. 8 and 9) according to claim 6.
Jia/Lee discloses wherein each dummy structure is made of an insulating material or a conductive material (Lee, each dummy structure is made of an insulating material or a conductive material, [0159], Figs. 8 and 9; Jia, each dummy structure is made of an insulating material or a conductive material, [0120], Figs. 1(a), 8, and 9); and
the conductive material comprises the same conductive material as the first signal wires (Lee, conductive material comprises the same conductive material as the first signal wires 440 (i.e. transparent conductive oxide), [0159], Figs. 8 and 9; Jia, each dummy structure is made of an insulating material or a conductive material, [0120], Figs. 1(a), 8, and 9).
Claim 16, Jia/Lee discloses the display substrate (Jia, display substrate 10/20, [0036], Figs. 1(a), 8, and 9; Lee, display apparatus 1 includes a display substrate, [0130], Figs. 8 and 9) according to claim 4.
Jia/Lee discloses wherein the dummy structure is made of an insulating material (Lee, dummy structure, [0159], Figs. 8 and 9; Jia, dummy structure is made of an insulating material, [0120], Figs. 1(a), 8, and 9).
Claim 17, Jia/Lee discloses the display substrate (Jia, display substrate 10/20, [0036], Figs. 1(a), 8, and 9; Lee, display apparatus 1 includes a display substrate, [0130], Figs. 8 and 9) according to claim 1.
Jia/Lee discloses wherein the pixel driver circuit further comprises a plurality of second signal wires in a same layer on the base (Lee, pixel driver circuit PC further comprises a plurality of second signal wires 420 in a same layer (i.e. input sensing layer 40) on the base 101, [0159] and [0161], Figs. 8 and 9; Jia, pixel driver circuit 20 further comprises a plurality of second signal wires 21 in a same layer on the base 10, [0088], Figs. 1(a), 8, and 9);
the plurality of second signal wires have the same extending direction (Lee, plurality of second signal wires 420 have the same extending direction (i.e. y-direction), [0159] and [0161], Figs. 8 and 9; Jia, pixel driver circuit 20 further comprises a plurality of second signal wires 21 in a same layer on the base 10, [0088], Figs. 1(a), 8, and 9);
the extending direction of the second signal wires forms acute angles greater than 0o and smaller than 90o with a length direction and a width direction of the strip, respectively (Lee, extending direction of the second signal wires 420 forms acute angles greater than 0o and smaller than 90o with a length direction (i.e. x-direction) and a width direction (i.e. y-direction) of the strip, respectively, [0159] and [0161], Figs. 8 and 9; Jia, pixel driver circuit 20 further comprises a plurality of second signal wires 21 in a same layer on the base 10, [0088], Figs. 1(a), 8, and 9);
the second signal wires are on a side of the first signal wires close to the base (Lee, second signal wires 420 are on a side of the first signal wires 440 close to the base 101, [0159] and [0161], Figs. 8 and 9; Jia, pixel driver circuit 20 further comprises a plurality of second signal wires 21 in a same layer on the base 10, [0088], Figs. 1(a), 8, and 9); and
an insulation layer is further provided between the second signal wires and the first signal wires (Lee, insulation layer 430 is further provided between the second signal wires 420 and the first signal wires 440, [0159] and [0161], Figs. 8 and 9; Jia, pixel driver circuit 20, [0088], Figs. 1(a), 8, and 9).
Claim 18, Jia/Lee discloses the display substrate (Jia, display substrate 10/20, [0036], Figs. 1(a), 8, and 9; Lee, display apparatus 1 includes a display substrate, [0130], Figs. 8 and 9) according to claim 17.
Jia/Lee discloses wherein the extending direction of the first signal wires forms angles of 40o to 50o with the length direction and the width direction of the strip, respectively (Lee, extending direction of the first signal wires 440 forms angles of 40o to 50o with the length direction and the width direction of the strip, respectively, [0159], Figs. 8 and 9; Jia, first signal wires 21 [0120], Figs. 1(a), 8, and 9); and
the extending direction of the second signal wires forms angles of 40o to 50o with the length direction and the width direction of the strip, respectively (Lee, extending direction of the second signal wires 420 forms angles of 40o to 50o with the length direction and the width direction of the strip, respectively, [0159], Figs. 8 and 9; Jia, second signal wires 21 [0120], Figs. 1(a), 8, and 9).
Claim 19, Jia/Lee discloses the display substrate (Jia, display substrate 10/20, [0036], Figs. 1(a), 8, and 9; Lee, display apparatus 1 includes a display substrate, [0130], Figs. 8 and 9) according to claim 1.
Jia/Lee discloses wherein the first electrodes each have a shape comprising any one of rectangle, diamond, ellipse, or trapezoid (Lee, first electrodes 440 each have a trapezoid shape, [0159] and [0161], Figs. 8, 9, and 14; Jia, first electrodes 50 each have a rectangle shape, [0088], Figs. 1(a), 8, and 9).
Claim 20, Jia/Lee discloses the display substrate (Jia, display substrate 10/20, [0036], Figs. 1(a), 8, and 9; Lee, display apparatus 1 includes a display substrate, [0130], Figs. 8 and 9) according to claim 18.
Jia/Lee discloses wherein the first signal wires comprise data lines or power lines or gate lines (Lee, first signal wires 440 comprise data lines or power lines or gate lines, [0159] and [0161], Figs. 8 and 9; Jia, first signal wires 21 comprise data lines or power lines or gate lines, [0088], Figs. 1(a), 8, and 9); and
the second signal wires comprise gate lines or data lines or power lines (Lee, second signal wires 420 comprise gate lines or data lines or power lines, [0159] and [0161], Figs. 8 and 9; Jia, second signal wires 21 comprise gate lines or data lines or power lines, [0088], Figs. 1(a), 8, and 9).
Claim 23, Jia/Lee discloses a display panel, comprising the display substrate (Jia, display substrate 10/20, [0036], Figs. 1(a), 8, and 9; Lee, display apparatus 1 includes a display substrate, [0130], Figs. 8 and 9) according to claim 1.
Jia/Lee discloses further comprising a pixel defining layer, an emission functional layer, and a second electrode (Jia, second planarization sub-layer 302 is a pixel defining layer, hereinafter, pixel defining layer 302, a light-emitting functional layer 60 is an emission functional layer, hereinafter, emission functional layer 60, and a second electrode 70, [0036], Figs. 1(a), 8, and 9; Lee, pixel defining layer 119, an emission functional layer 50, and a second electrode 440, [0130], Figs. 8 and 9); wherein
the pixel defining layer, the emission functional layer and the second electrode are sequentially stacked on a side of the first electrodes in the display substrate away from the pixel driver circuit (Jia, pixel defining layer 302, emission functional layer 60, and a second electrode 70 are sequentially stacked on a side of the first electrodes 50 in the display substrate 10/20 away from the pixel driver circuit 20, [0036], Figs. 1(a), 8, and 9; Lee, pixel defining layer 119, an emission functional layer 50, and a second electrode 420 are sequentially stacked on a side of the first electrodes 440 in the display substrate away from the pixel driver circuit PC, [0130], Figs. 8 and 9); and
the pixel defining layer is provided with a plurality of openings from which the first electrodes are partially exposed (Jia, pixel defining layer 302 is provided with a plurality of openings from which the first electrodes 50 are partially exposed, [0036], Figs. 1(a), 8, and 9; Lee, pixel defining layer 119 is provided with a plurality of openings from which the first electrodes 440 are partially exposed, [0130], Figs. 8 and 9), and orthographic projections of the emission functional layer and the second electrode on the pixel driver circuit cover at least orthographic projections of the openings on the pixel driver circuit (Jia, orthographic projections of the emission functional layer 60 and the second electrode 70 on the pixel driver circuit 20 cover at least orthographic projections of the openings on the pixel driver circuit 20, [0036], Figs. 1(a), 8, and 9; Lee, orthographic projections of the emission functional layer 50 and the second electrode 420 on the pixel driver circuit PC cover at least orthographic projections of the openings on the pixel driver circuit PC, [0130], Figs. 8 and 9).
Claim 24, Jia/Lee discloses a display apparatus (Jia, display substrate 10/20 is used to form a resultant display apparatus, [0036], Figs. 1(a), 8, and 9; Lee, display apparatus 1, [0130], Figs. 8 and 9), comprising the display panel according to claim 23 (Jia, display substrate 10/20 is used to form a resultant display apparatus and may comprise the display panel, [0036], Figs. 1(a), 8, and 9; Lee, display apparatus 1 comprises the display panel, [0130], Figs. 8 and 9).
Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Jia in view of Lee, and further in view of Moon (US 2022/0149132 A1).
Claim 10, Jia/Lee discloses the display substrate (Jia, display substrate 10/20, [0036], Figs. 1(a), 8, and 9; Lee, display apparatus 1 includes a display substrate, [0130], Figs. 8 and 9) according to claim 9.
Jia/Lee does not explicitly disclose wherein each first electrode is a uniformly concaved layer.
However, Moon discloses wherein each first electrode is a uniformly concaved layer (Moon, each first electrode 330 is a uniformly concaved layer, [0108], Fig. 14; Lee, wherein each first electrode 440 is a uniformly concaved layer, [0159] and [0161], Figs. 8, 9, and 14; Jia, wherein each first electrodes 50 is a uniformly concaved layer, [0088], Figs. 1(a), 8, and 9). The combination to utilize a first electrode which is a uniformly concaved layer enables the resultant integration degree to be improved, and high performance may be secured (Moon, [0195]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize a first electrode which is a uniformly concaved layer to enable the resultant integration degree to be improved, and high performance to be secured (Moon, [0195]).
Claim 11, Jia/Lee/Moon discloses the display substrate (Jia, display substrate 10/20, [0036], Figs. 1(a), 8, and 9; Lee, display apparatus 1 includes a display substrate, [0130], Figs. 8 and 9; Moon, display apparatus, Fig. 14) according to claim 10.
Jia/Lee/Moon discloses wherein the orthographic projections of adjacent first signal wires on the base, the orthographic projections of each dummy structure and an adjacent first signal wire on the base, and the orthographic projections of adjacent dummy structures on the base, are spaced by a distance equal to an average line width of the plurality of first signal wires, respectively (Lee, the orthographic projections of adjacent first signal wires 440 on the base 101, the orthographic projections of each dummy structure and an adjacent first signal wire 440 on the base 101, and the orthographic projections of adjacent dummy structures on the base 101, are spaced by a distance equal to an average line width of the plurality of first signal wires 440, respectively, [0159], Figs. 8 and 9; Jia, the orthographic projections of adjacent first signal wires 21 on the base 10, the orthographic projections of each dummy structure and an adjacent first signal wire 21 on the base 10, and the orthographic projections of adjacent dummy structures on the base 10, are spaced by a distance equal to an average line width of the plurality of first signal wires 21, respectively, [0120], Figs. 1(a), 8, and 9; Moon, display apparatus, Fig. 14); and
a width of each dummy structure in an arrangement direction of the plurality of first signal wires is equal to the average line width of the plurality of first signal wires (Lee, a width of each dummy structure in an arrangement direction of the plurality of first signal wires 440 is equal to the average line width of the first signal wires 440, [0159], Figs. 8 and 9; Jia, a width of each dummy structure in an arrangement direction of the plurality of first signal wires 21 is equal to the average line width of the first signal wires 21 [0120], Figs. 1(a), 8, and 9; Moon, display apparatus, Fig. 14).
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Jia in view of Lee, and further in view of Bok (US 2021/0191552 A1).
Claim 21, Jia/Lee discloses the display substrate (Jia, display substrate 10/20, [0036], Figs. 1(a), 8, and 9; Lee, display apparatus 1 includes a display substrate, [0130], Figs. 8 and 9) according to claim 15.
Jia/Lee discloses wherein each dummy structure is made of a conductive material (Lee, each dummy structure is made of a conductive material, [0159], Figs. 8 and 9; Jia, each dummy structure is made of a conductive material, [0120], Figs. 1(a), 8, and 9) and connected to a first potential signal or a second potential signal (Lee, each dummy structure is connected to a first potential signal or a second potential signal, [0159], Figs. 8 and 9; Jia, each dummy structure is connected to a first potential signal or a second potential signal, [0120], Figs. 1(a), 8, and 9).
Jia/Lee does not explicitly disclose the first potential signal is greater than the second potential signal; the second potential signal is greater than or equal to a ground potential; and the first potential signal comprises a potential of a power line.
However, Bok discloses the first potential signal is greater than the second potential signal; the second potential signal is greater than or equal to a ground potential; and the first potential signal comprises a potential of a power line (Bok, first potential signal is greater than the second potential signal, the second potential signal is greater than or equal to a ground potential, and the first potential signal comprises a potential of a power line, [0560] and [0562], Fig. 1; Jia, display substrate 10/20, [0036], Figs. 1(a), 8, and 9; Lee, display apparatus 1 includes a display substrate, [0130], Figs. 8 and 9). The utilization of two potential signals, in addition to a ground potential, allows for generation and transmission of data signals to the pixel circuits and peripheral circuitry (Bok, [0562]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize two potential signals, in addition to a ground potential, to allow for generation and transmission of data signals to the pixel circuits and peripheral circuitry (Bok, [0562]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kim (US 2022/0263045 A1) discloses a display substrate 101, comprising a pixel driver circuit PC and a plurality of first electrodes 121 on the pixel driver circuit PC, wherein
the pixel driver circuit PC comprises a base TFT, and a plurality of first signal wires CE1 in a same layer on the base TFT;
the plurality of first signal wires CE1 have the same extending direction;
the first electrodes 121 and the first signal wires CE1 are in different layers;
orthographic projections of the first signal wires CE1 on the base TFT are partially overlapped with orthographic projections of the first electrodes 121 on the base TFT;
the first electrodes 121 each have a strip shape, and the plurality of first electrodes 121 are arranged in an array along a length direction and a width direction of the strip shape;
the display substrate further comprises an auxiliary leveling structure 113 on a side of the first signal wires CE1 away from the base TFT and a side of the first electrodes 121 close to the base TFT, and an orthographic projection of the auxiliary leveling structure 113 on the base TFT covers at least the orthographic projections of the first electrodes 121 on the base TFT; and
the auxiliary leveling structure 113 enables a layer of the first electrodes 121 flat.
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/CHEVY J BOEGEL/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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