Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Office Action is in response to the Applicant’s communication filed on 25 July 2024. In virtue of this communication, claims 1-24 are currently presented in the instant application. In light of a preliminary amendment on 25 July 2024, claims 1-12 have been cancelled, and claims 1-13 have been newly added.
Information Disclosure Statement(s)
The information disclosure statement(s) (IDS) submitted on 25 July 2024 is/are in compliance with the provisions of 37 CFR 1.97 and 1.98. Accordingly, the information disclosure statement(s) is/are being considered by the examiner.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 13 and 17-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kido et al. (Publication No.: JP 2008249452 A, herein known as D1, a machine translation is provided with this Office Action) in view of Yokotani et al. (Patent No.: US 5,789,925 A, herein known as D2).
With respect to claim 13, D1 discloses an evaluation circuit for a passive rotational speed sensor of a vehicle, the passive rotational speed sensor being configured to detect a rotational speed of an automotive part and to generate a sensor signal based thereon (technical field: the present invention relates for detecting a change in a magnetic field for a magnetic detection device suitable for use in detecting rotation information), comprising:
a first connection and second connection for the electrical connection of the rotational speed sensor (see Fig. 3, Vamp or its previous connections and Vref or its previous connections, such as magnetoresistive element bridge 120 which is described as a wheatstone bridge connected to power and ground);
a comparator which is connected to the first connection and the second connection and is configured to compare the sensor signal with a reference voltage, and to generate a pulsating output signal based on the comparison (comparison circuit 160 which has Vamp which is the sensor signal and Vref as the reference voltage as the two connection inputs);
an operational amplifier configured as a buffer circuit to maintain the reference voltage at a predetermined level (reference voltage generation circuit 180 includes a low pass-pass filter 184 and buffer 186 which outputs the Vref voltage); and
a first signal output, wherein the first signal output is connected to an output of the comparator (Vpls of Fig. 3) in order to provide the pulsating output signal for determining the rotational speed of the wheel (Vpls is output to the output circuit 240, which outputs Vout, which “it is easy to accurately count the number of pulses of the output signal Vout of the magnetic detection device 100, and the accuracy when detecting the rotational speed and rotational position of the soft magnetic gear 1 is improved.”).
D1 does not explicitly disclose being able to measure the rotational speed of a wheel (D1 explicitly cites “a magnetic detection device suitable for use in detecting rotation information of a soft magnetic gear used in industrial machine tools, automobile engines, and the like”). It is also noted that the present application states “The wheel can be any wheel, such as a magnetic wheel coupled to a braked wheel or a gear wheel (e.g. in the gearbox).” [Examiner’s emphasis].
However, one of ordinary skill in the art would recognize how the “magnetic gear used in the automobile engine” would include the gear wheel of the engine as an obvious choice to be measured using the circuit of D1 without requiring any undue experimentation. Alternatively, it is known to be able to determine the wheel’s RPM from the engine RPM (wheel RPM = engine RPM/transmission ratio), and D1 measuring the engine RPM will allow a determination of the wheel’s RPM.
D1 does not disclose a second signal output for redundantly providing the pulsating output signal.
D2 teaches a speed sensor for a vehicle (column 1 lines 7-9) that utilizes three output lines (25 and 26, Vout 1 and Vout 2, and 27, a fail). The two Vouts are utilized to ensure safety should one of the wires fail (Column 5 lines 11-15), and the fail output is utilized to detect for abnormalities in the system (Column 4 lines 26-28).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the circuit of D1 by utilizing the additional output of D2 in the form of a secondary redundant output line in order to provide additional safety in case of a wire failure, an additional circuit for failure/abnormality detection, or both.
With respect to claim 17, the combination of D1 and D2 further discloses a circuit wherein the circuit has at least one of the following inputs or outputs: a test signal input for feeding in a test signal, wherein the test signal input is connected to the first connection and/or to the second connection, and/or a first status signal output connected to the first connection, and/or a second status signal output connected to the second connection (D2: wire 27 is a fail signal as described above; this combination incorporates the abnormality detection of D2 into the circuit of D1 as described in the combination above).
With respect to claim 18, the combination of D1 and D2 further discloses a circuit further comprising: a control unit configured to receive signals from one or more of the following ports: the first signal output, the second signal output, the first status signal output, the second status signal output, and/or the test signal input; wherein the control unit is further configured to monitor the passive rotational speed sensor based on the received signals (in the combination output circuit 240 of D1 would be obviously modified to receive the extra outputs from the teachings of D2, which similarly teaches a CPU 29 to process the signals from Vout1, Vout2, and FAIL).
With respect to claim 19, the combination of D1 and D2 further discloses wherein the control unit is further configured to detect at least one of the following faults: a short circuit of the first connection to ground, a short circuit of the second connection to ground, a short circuit of the first connection to a supply voltage, a short circuit of the second connection to a supply voltage, a short circuit between the first connection and the second connection, a crosstalk between the first connection and the second connection or a crosstalk between an external signal line to the first connection or to the second connection, and/or an open electrical connection at the first connection or at the second connection; wherein the detection is based on signals at at least one of the following outputs: the first status signal output, the second status signal output, the first signal output, and/or the second signal output (in the combination output circuit 240 of D1 would be obviously modified to receive the extra outputs from the teachings of D2, which similarly teaches a CPU 29 to process the signals from Vout1, Vout2, and FAIL; and it would have further been obvious to incorporate the detection of the abnormalities into the combination, which allows for the detection of disconnection, short-circuiting, or the like as described in D2 Column 6 lines 11-20).
With respect to claim 20, the combination of D1 and D2 further discloses a circuit wherein the first connection or the second connection is connected to a supply connection, so that in a fault-free state a voltage drops across the first connection and the second connection even when the wheel is stationary, wherein the control unit is configured to detect the fault by a measurement of the voltage at the first connection or at the second connection using the first status signal output or the second status signal output, and wherein the control unit is further configured to feed in a test signal at the test signal input or not to feed in a test signal (this would appear to be inherent or at least obvious within the combination as described in D2 Column 5 line 57 – Column 6 line 20 in which by being connected to the Vcc and GND lines 28, as would be done in the combination, detections can be measured and determined).
With respect to claim 21, the combination of D1 and D2 further discloses a circuit wherein a low-pass filter is formed at at least one of the following outputs and connections: the first signal output, the second signal output, the first status signal output, the second status signal output, and/or between the first connection and the second connection (D1 low pass filter 184 is between the first connection and second connection.
With respect to claim 22, see the rejection of claim 13 above (being incorporated into an ABS system is considered an intended use and would have been obvious to one of ordinary skill in the art as the combination teaches a mechanism to detect the wheel speed, and there does not seem to be any structural differences that distinguishes the circuit being used in an ABS system vs any other system).
With respect to claim 23, see the rejection of claim 13 above (the method of reading out the signals from the evaluation circuit to determine the rotational speed is taught by D1 “That is, for example, it is easy to accurately count the number of pulses of the output signal Vout of the magnetic detection device 100, and the accuracy when detecting the rotational speed and rotational position…”).
With respect to claim 24, see the rejection of claim 19 above (the method of D2 teaches using the signal detected to determine short-circuits, disconnections, and other abnormalities as described in D2 Column 6 lines 11-20).
Claim(s) 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of D1 and D2 as applied to claim 13 above, and further in view of Jackson (Publication No.: US 2005/0286182 A1, herein known as D3).
With respect to claim 14, the combination of D1 and D2 does not disclose a circuit further comprising: a voltage limiter configured to limit an input voltage at the comparator to its input voltage range.
D3 teaches a voltage limiter connected to the input of a comparator to prevent the input signal from exceeding a predetermined voltage ([0107]).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to further modify the circuit of the combination of D1 and D2 to utilize a voltage limiter connected to the input of the comparator as taught by D3 to prevent the signal from exceeding a predetermined voltage for the circuit to operate properly.
With respect to claim 15, the combination of D1, D2, and D3 further discloses a circuit wherein the operational amplifier is configured as a voltage follower so that the reference voltage for the comparator is available at low impedance (D1: “The buffer 186 is not particularly limited, but here, a voltage follower that directly connects the inverting input terminal and the output terminal of the operational amplifier and outputs the voltage of the non-inverting input terminal (the voltage at the connection point of the resistor R8 and the capacitor C) from the output terminal is used.”).
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of D1, D2, and D3 as applied to claim 15 above, and further in view of Vladimir et al. (Publication No.: KR 20160027186 A, herein known as D4, a machine translation is provided with this Office Action).
With respect to claim 16, the combination of D1, D2, and D3 further discloses a a circuit wherein the operational amplifier includes a sensor signal input, a reference signal input, and an output, and wherein the sensor signal input is connected to the output, and wherein the voltage limiter has a diode connected to the output to safely limit and input voltage of the comparator to its input voltage range (see combination, D1 shows the operational amplifier buffer 186 which has the signal input and output arrangement as seen in Fig. 3, and Fig. 4 of D3 shows the voltage limiter as a single diode arrangement).
The combination of D1, D2, and D3 does not disclose a circuit wherein the voltage limiter has two back-to-back-connected diodes, and a current node between the back-to-back-connected diodes is connected to the output of the operational amplifier to safely limit an input voltage of the comparator to its voltage range.
D4 teaches a voltage limiter arranged with a back-to-back diode arrangement as described (see Fig. 1). D4 also describes advantages for the arrangement such as protecting the circuit against surges (abstract, technical field).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to further modify the circuit of the combination of D1, D2, and D3 by utilizing the back-to-back diode and current node of D4 as a known enhanced voltage limiter circuit that also has advantages such as preventing against surges as described.
Citation of Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Frenzel et al. (Patent No.: US 11,400,901 B2)
Meyer (Publication No.: US 2019/0064197 A1)
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DIANA HANCOCK whose telephone number is (571)270-7547. The examiner can normally be reached on 10AM-6PM EST M-F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Stephanie Bloss can be reached on (571) 272-3555. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/D.H/Examiner, Art Unit 2852
8/31/2026
/STEPHANIE E BLOSS/Supervisory Primary Examiner, Art Unit 2852
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