DETAILED ACTION
The following claims are pending in this office action: 1-20
Claim 1, 11 and 20 are independent claims
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings filed on 07/26/2024 are accepted.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 07/26/2024 and 08/08/2024 have been considered. The submissions are in compliance with the provisions of 37 CFR 1.97. Accordingly, initialed and dated copies of Applicant’s IDS forms 1449 filed 07/26/2024 and 08/08/2024 are attached to the instant Office action.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4, 6-11, 14 and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Arisawa et al. (US Pub. 2005/0201552) (hereinafter “Arisawa”) in view El-Alfy et al. (US Pub. 2018/0054301) (hereinafter “El-Alfy”).
As per claim 1, Arisawa teaches a computer-implemented method, comprising: ([Arisawa, para. 0002] “present invention generally relates to a data processing circuit and a control method therefor”)
storing, with a device, at least one secret value; ([Arisawa, para. 0029] “Fig. 1 illustrates an IP chip [a device]”; [para. 0031] “an encryption key used for encryption ... supplied [storing] to an encryption processing circuit [with a device as the circuit is part of the device – see Fig. 1]”)
executing, with a cryptographic subsystem of the device, at least one cryptographic operation based on the at least one secret value; ([Arisawa, para. 0032] “The encryption processing circuit 1 [with a cryptographic subsystem of the device – see Fig. 1] encrypts [executing at least one cryptographic operation] the supplied plaintext data using the supplied encryption key [based on the at least one secret value]”)
storing, with an artificial sequence generator, at least one state indication; ([Arisawa, para. 0042-0043] “The security level for encryption [state indication] performed by the encryption processing circuit... supplied ... preset in the IC chip”; [Fig .1] the security level is stored in the noise generation circuit; the security level is congruent with the broadest reasonable interpretation of “state indication” in view of the specification as it is a pattern/state/feature – see para. 0081 of the instant specification)
generating, with the artificial sequence generator, a plurality of samples of artificial noise, ([Arisawa, para. 0039; Fig. 1] “the oscillator 10n [part of the artificial sequence generator – see Fig. 1] drives the noise generator 11n according to a control signal from the control circuit 14, where n=1, 2, . . . , N ... [a plurality of] The noise generator 11n is driven by the oscillator 10n to generate ... pseudo-random noise [artificial noise]”) wherein a number of the plurality of samples is based on at least one power constraint parameter; and ([para. 0038; Fig. 1] “The noise generation circuit 5 calculates the sum of a plurality of independent signals (currents) [at least one power constraint parameter in view of the BRI of the spec – see para. 0072 describing the parameter as a current component] to generate a noise”)
overlaying, with the artificial sequence generator, each sample of artificial noise of the plurality of samples of artificial noise ([Arisawa, para. 0045; Fig. 1] “In the noise generation circuit 5 [with the artificial sequence generator], the currents [each sample of artificial noise – see Fig. 1] ... are summed [overlaying] ... a resulting noise current In”) over a respective portion of a side channel signal ([para. 0050] “superimposing the noise current In generated by the noise generation circuit 5 on the current Ides [a portion of a side channel signal – see para. 0050: “current I that can be observed outside the IC chip”] consumed by the encryption processing circuit 1”) based on the at least one state indication ([para. 0055] “The control circuit 14 controls the number of independent currents to be summed for generating a noise current depending upon the security level [based on the at least one state indication]”) to mask leakage information associated with the at least one secret value on the side channel signal. ([Para. 0050] Therefore, the current I that can be observed outside the IC chip [leakage information] is determined by superimposing the noise current In on the consumed current Ides, rather than the current Ides [on the side channel signal] consumed by the encryption processing circuit 1 [associated with the at least one secret value], thus preventing an intermediate key from being broken by DPA attacks based on analysis of the consumed current Ides [masking leakage information] to provide high security”)
Arisawa does not clearly teach at least one secret value comprising secret value bits; and at least one state indication based on a plurality of previous cryptographic operations executed on the device.
However, El-Alfy teaches at least one secret value comprising secret value bits; and ([El-Alfy, para. 0036] “the key ... 256 bits”)
at least one state indication ([El-Alfy, para. 0002] “the security level of a cryptographic system depends on the complexity involved [based upon previous cryptographic operations]”) based on a plurality of previous cryptographic operations executed on the device. ([para. 0054] “states Si are calculated by adding the previous state Si−1 [previous cryptographic operations executed on the device] to the numeric value of K”; [para. 0056] “a key stream [at least one state indication] is generated based on the above generated states Si [previous cryptographic operations executed on the device]”)
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to have modified the elements disclosed by Arisawa with the teachings of El-Alfy to include at least one secret value comprising secret value bits; and at least one state indication based on a plurality of previous cryptographic operations executed on the device. One of ordinary skill in the art would have been motivated to make this modification because the scheme eliminates the vulnerability to known-plaintext attack improving the security of communications between computer systems. (El-Alfy, para. 0049)
As per claim 4, Arisawa in view of El-Alfy teaches claim 1.
Arisawa also teaches wherein the at least one state indication comprises a plurality of state indications, each state indication of the plurality of state indications associated with a respective time ([Arisawa, para. 0056; para. 0059] “When the security level is low [first state indication] ... the control circuit 14 controls ... noise generators ... When the security level is high [another state indication] ... the control circuit 14 controls ... noise generators”; [para. 0082] “a noise current [making the state indications “associated” with the following as the state indications is associated with generation of the noise current] is superimposed at a timing [a respective time]”) that the cryptographic subsystem is processing the at least one secret value during execution of the at least one cryptographic operation, and ([para. 0082] “a noise current is superimposed for periods of time [respective time] including the rising edges of the master clock MCLK at which the encryption processing circuit 1 [cryptographic subsystem] shown in FIG. 1 is activate [processing the at least one secret value during execution of the at least one cryptographic operation]”)
wherein overlaying each sample of artificial noise of the plurality of samples of artificial noise comprises ([Arisawa, para. 0045; Fig. 1] “In the noise generation circuit 5 [with the artificial sequence generator], the currents [each sample of artificial noise – see Fig. 1] ... are summed [overlaying] ... a resulting noise current In”) overlaying each sample of artificial noise over the respective portion of the side channel signal ([para. 0050] “superimposing the noise current In generated by the noise generation circuit 5 on the current Ides [a portion of a side channel signal] consumed by the encryption processing circuit 1”) based on the respective time that the cryptographic subsystem is processing the at least one secret value. ([Para. 0082] “a noise current is superimposed [the overlaying] for periods of time [based on the respective time] including the rising edges of the master clock MCLK at which the encryption processing circuit 1 [cryptographic subsystem] shown in FIG. 1 is activate [is processing the at least one secret value]”)
As per claim 6, Arisawa in view of El-Alfy teaches claim 1.
Arisawa also teaches further comprising predicting with the artificial sequence generator, an approximate time during which the cryptographic subsystem will be executing the at least one cryptographic operation. ([Arisawa, para. 0073] “the timing signal ... is set ... in the vicinity of [predicting/an approximate time] the rising edge of the master clock”; [para. 0094] “The noise current In' ... is caused to flow [predicting with the artificial sequence generator as the generator generates the noise/flow of the noise] only for a period of time [an approximate time] during which the switch 4 is turned according to the timing signal IT [during which the cryptographic system will be executing]”; [para. 0082] “the encryption processing circuit 1 shown in FIG. 1 is activated, [cryptographic subsystem will be executing the at least one cryptographic operation] that is, for periods of time during which the timing signal IT is set to the logical "1" level [time during which]”)
Arisawa does not clearly teach executing the at least one cryptographic operation based on the at least one state indication.
However, El-Alfy teaches executing the at least one cryptographic operation based on the at least one state indication. ([El-Alfy, para. 0056-0057] “a key stream is generated based on the above generated states Si [based on the at least one state indication] ... The key stream ... used to encrypt the plaintext [executing the at least one cryptographic operation]”)
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Arisawa and El-Alfy for the same reasons as disclosed above.
As per claim 7, Arisawa in view of El-Alfy teaches claim 6.
Arisawa also teaches wherein predicting the approximate time, comprises: ([Arisawa, para. 0094] “The noise current In' ... is caused to flow [predicting with the artificial sequence generator as the generator generates the noise/flow of the noise] only for a period of time [an approximate time]”)
generating the plurality of samples of artificial noise based on a random vector ([Arisawa, para. 0049] “the independent currents caused by the current sources 131 to 13N to flow ... current whose distribution approaches the Gaussian distribution [vector], that is, a noise current which is ... random [random vector]”) and a sample rate for overlaying each sample of artificial noise over the respective portion of the side channel signal. ([para. 0082] “a noise current is superimposed [for overlaying each sample] at a timing at which a difference in the consumed current Ides [over the respective portion of the side channel signal] between the logical "0" and "1" levels occurs [sample rate]”; Fig. 4 depicts the sampling rate for the noise current In’)
As per claim 8, Arisawa in view of El-Alfy teaches claim 1.
Arisawa also teaches further comprising: selecting a number of the plurality of samples of artificial noise based on a rank of a selection matrix and the at least one power constraint. ([Arisawa, para. 0046] “The switch 12n [a number of the plurality of samples of artificial noise – see Fig. 1] ... is turned on or off [selecting a number of samples] according to ... the oscillator 10n [a rank of a selection matrix] .... the current source 13n [at least one power constraint]”; [para. 0069] “oscillators 101 to 10N to the number [a rank] indicated by the control signal from the control circuit 14 [of a selection matrix]”)
As per claim 9, Arisawa in view of El-Alfy teaches claim 1.
Arisawa also teaches wherein a leakage trace available on a side channel of the side channel signal comprises a linear combination of an original leakage trace resulting from the cryptographic subsystem executing the at least one cryptographic operation, naturally occurring noise on the side channel, and the plurality of samples of artificial noise. ([Arisawa, para. 0066] “In the IC chip shown in FIG. 1, the consumed current Ides [original leakage trace] flows to the encryption processing circuit 1 from the power supply line L [naturally occurring noise on the side channel] ... The noise current In'[plurality of samples of artificial noise] flows to the noise generation circuit 5 from the power supply line L ...The current I [leakage trace available on a side channel of the side channel signal] flowing [comprising] in the power supply line L [natural occurring noise] is therefore represented by the sum of [linear combination of] the consumed current Ides [original leakage trace]and the noise current In'[plurality of samples]; [Fig. 1] Fig. 1 shows the current output from the VDD power supply is a function of the natural current supplied, current of the encryption circuit, and current of the noise generation circuit)
As per claim 10, Arisawa in view of El-Alfy teaches claim 1.
Arisawa also teaches wherein the side channel signal comprises a power sign or an electromagnetic signal. ([Arisawa, para. 0050] “Therefore, the current I that can be observed outside the IC chip [side channel signal] is determined by superimposing the noise current In [comprises a power sign or an electromagnetic signal]”)
As per claim 11, Arisawa teaches a system, comprising:
at least one processor to: ([Arisawa, para. 0002] “present invention generally relates to a data processing circuit and a control method therefor”)
store at least one secret value; ([Arisawa, para. 0029] “Fig. 1 illustrates an IP chip”; [para. 0031] “an encryption key used for encryption ... supplied [storing] to an encryption processing circuit”)
execute at least one cryptographic operation based on the at least one secret value; ([Arisawa, para. 0032] “The encryption processing circuit 1 encrypts [executing at least one cryptographic operation] the supplied plaintext data using the supplied encryption key [based on the at least one secret value]”)
store at least one state indication; ([Arisawa, para. 0042-0043] “The security level for encryption [state indication] performed by the encryption processing circuit... supplied ... preset in the IC chip”; [Fig .1] the security level is stored in the noise generation circuit; the security level is congruent with the broadest reasonable interpretation of “state indication” in view of the specification as it is a pattern/state/feature – see para. 0081 of the instant specification)
generate a plurality of samples of artificial noise, ([Arisawa, para. 0039; Fig. 1] “the oscillator 10n drives the noise generator 11n according to a control signal from the control circuit 14, where n=1, 2, . . . , N ... [a plurality of] The noise generator 11n is driven by the oscillator 10n to generate ... pseudo-random noise [artificial noise]”) wherein a number of the plurality of samples is based on at least one power constraint parameter; and ([para. 0038; Fig. 1] “The noise generation circuit 5 calculates the sum of a plurality of independent signals (currents) [at least one power constraint parameter in view of the BRI of the spec – see para. 0072 describing the parameter as a current component] to generate a noise”)
overlay each sample of artificial noise of the plurality of samples of artificial noise ([Arisawa, para. 0045; Fig. 1] “In the noise generation circuit 5, the currents [each sample of artificial noise – see Fig. 1] ... are summed [overlaying] ... a resulting noise current In”) over a respective portion of a side channel signal ([para. 0050] “superimposing the noise current In generated by the noise generation circuit 5 on the current Ides [a portion of a side channel signal – see para. 0050: “current I that can be observed outside the IC chip”] consumed by the encryption processing circuit 1”) based on the at least one state indication ([para. 0055] “The control circuit 14 controls the number of independent currents to be summed for generating a noise current depending upon the security level [based on the at least one state indication]”) to mask leakage information associated with the at least one secret value on the side channel signal. ([Para. 0050] Therefore, the current I that can be observed outside the IC chip [leakage information] is determined by superimposing the noise current In on the consumed current Ides, rather than the current Ides [on the side channel signal] consumed by the encryption processing circuit 1 [associated with the at least one secret value], thus preventing an intermediate key from being broken by DPA attacks based on analysis of the consumed current Ides [masking leakage information] to provide high security”)
Arisawa does not clearly teach at least one non-transitory computer readable medium comprising one or more instructions that, when executed by the at least one processor, cause the processor to perform a method; at least one secret value comprising secret value bits; and at least one state indication based on a plurality of previous cryptographic operations executed on a device.
However, El-Alfy teaches at least one non-transitory computer readable medium comprising one or more instructions that, when executed by the at least one processor, cause the processor to perform a method; ([El-Alfy, para. 0012] “the disclosure provide a non-transitory computer readable storage medium having computer readable instructions stored thereon ... The instructions, when executed by processing circuitry, cause the processing circuitry to perform a method”)
at least one secret value comprising secret value bits; and ([El-Alfy, para. 0036] “the key ... 256 bits”)
at least one state indication ([El-Alfy, para. 0002] “the security level of a cryptographic system depends on the complexity involved [based upon previous cryptographic operations]”) based on a plurality of previous cryptographic operations executed on a device. ([para. 0054] “states Si are calculated by adding the previous state Si−1 [previous cryptographic operations executed on the device] to the numeric value of K”; [para. 0056] “a key stream [at least one state indication] is generated based on the above generated states Si [previous cryptographic operations executed on the device]”)
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to have modified the elements disclosed by Arisawa with the teachings of El-Alfy to include at least one secret value comprising secret value bits; and at least one state indication based on a plurality of previous cryptographic operations executed on a device. One of ordinary skill in the art would have been motivated to make this modification because the scheme eliminates the vulnerability to known-plaintext attack improving the security of communications between computer systems. (El-Alfy, para. 0049)
As per claim 14, the claim language is identical or substantially similar to that of claim 4. Therefore, it is rejected under the same rationale applied to claim 4.
As per claim 16, the claim language is identical or substantially similar to that of claim 6. Therefore, it is rejected under the same rationale applied to claim 6.
As per claim 17, the claim language is identical or substantially similar to that of claim 7. Therefore, it is rejected under the same rationale applied to claim 7.
As per claim 18, the claim language is identical or substantially similar to that of claim 8. Therefore, it is rejected under the same rationale applied to claim 8.
As per claim 19, the claim language is identical or substantially similar to that of claim 9. Therefore, it is rejected under the same rationale applied to claim 9.
As per claim 20, Arisawa teaches at least one computing device to: ([Arisawa, para. 0002] “present invention generally relates to a data processing circuit and a control method therefor”)
store at least one secret value; ([Arisawa, para. 0029] “Fig. 1 illustrates an IP chip”; [para. 0031] “an encryption key used for encryption ... supplied [storing] to an encryption processing circuit”)
execute at least one cryptographic operation based on the at least one secret value; ([Arisawa, para. 0032] “The encryption processing circuit 1 encrypts [executing at least one cryptographic operation] the supplied plaintext data using the supplied encryption key [based on the at least one secret value]”)
store at least one state indication; ([Arisawa, para. 0042-0043] “The security level for encryption [state indication] performed by the encryption processing circuit... supplied ... preset in the IC chip”; [Fig .1] the security level is stored in the noise generation circuit; the security level is congruent with the broadest reasonable interpretation of “state indication” in view of the specification as it is a pattern/state/feature – see para. 0081 of the instant specification)
generate a plurality of samples of artificial noise, ([Arisawa, para. 0039; Fig. 1] “the oscillator 10n drives the noise generator 11n according to a control signal from the control circuit 14, where n=1, 2, . . . , N ... [a plurality of] The noise generator 11n is driven by the oscillator 10n to generate ... pseudo-random noise [artificial noise]”) wherein a number of the plurality of samples is based on at least one power constraint parameter; and ([para. 0038; Fig. 1] “The noise generation circuit 5 calculates the sum of a plurality of independent signals (currents) [at least one power constraint parameter in view of the BRI of the spec – see para. 0072 describing the parameter as a current component] to generate a noise”)
overlay each sample of artificial noise of the plurality of samples of artificial noise ([Arisawa, para. 0045; Fig. 1] “In the noise generation circuit 5, the currents [each sample of artificial noise – see Fig. 1] ... are summed [overlaying] ... a resulting noise current In”) over a respective portion of a side channel signal ([para. 0050] “superimposing the noise current In generated by the noise generation circuit 5 on the current Ides [a portion of a side channel signal – see para. 0050: “current I that can be observed outside the IC chip”] consumed by the encryption processing circuit 1”) based on the at least one state indication ([para. 0055] “The control circuit 14 controls the number of independent currents to be summed for generating a noise current depending upon the security level [based on the at least one state indication]”) to mask leakage information associated with the at least one secret value on the side channel signal. ([Para. 0050] Therefore, the current I that can be observed outside the IC chip [leakage information] is determined by superimposing the noise current In on the consumed current Ides, rather than the current Ides [on the side channel signal] consumed by the encryption processing circuit 1 [associated with the at least one secret value], thus preventing an intermediate key from being broken by DPA attacks based on analysis of the consumed current Ides [masking leakage information] to provide high security”)
Arisawa does not clearly teach a computer program product comprising at least one non- transitory computer-readable medium having instructions stored thereon that, when executed by at least one computing device, cause the at least one computing device to perform a method; at least one secret value comprising secret value bits; and at least one state indication based on a plurality of previous cryptographic operations executed on a device.
However, El-Alfy teaches a computer program product comprising at least one non- transitory computer-readable medium having instructions stored thereon that, when executed by at least one computing device, cause the at least one computing device to perform a method; ([El-Alfy, para. 0012] “the disclosure provide a non-transitory computer readable storage medium having computer readable instructions stored thereon ... The instructions, when executed by processing circuitry, cause the processing circuitry to perform a method”)
at least one secret value comprising secret value bits; and ([El-Alfy, para. 0036] “the key ... 256 bits”)
at least one state indication ([El-Alfy, para. 0002] “the security level of a cryptographic system depends on the complexity involved [based upon previous cryptographic operations]”) based on a plurality of previous cryptographic operations executed on the device. ([para. 0054] “states Si are calculated by adding the previous state Si−1 [previous cryptographic operations executed on the device] to the numeric value of K”; [para. 0056] “a key stream [at least one state indication] is generated based on the above generated states Si [previous cryptographic operations executed on the device]”)
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to have modified the elements disclosed by Arisawa with the teachings of El-Alfy to include at least one secret value comprising secret value bits; and at least one state indication based on a plurality of previous cryptographic operations executed on the device. One of ordinary skill in the art would have been motivated to make this modification because the scheme eliminates the vulnerability to known-plaintext attack improving the security of communications between computer systems. (El-Alfy, para. 0049)
Claims 2-3 and 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Arisawa in view El-Alfy as applied to claim 1 above, and further in view of Miller (US Pub. 2021/0224384) (hereinafter “Miller”) and Shvetsov et al. (US Pub. 2021/0400491) (hereinafter “Shvetsov”)
As per claim 2, Arisawa in view of El-Alfy teaches claim 1.
Arisawa also teaches wherein generating the plurality of samples of artificial noise comprises generating the plurality of samples of artificial noise based on a Gaussian random vector, ([Arisawa, para. 0047]” a summation signal obtained by summing a plurality of independent signals approaches the Gaussian distribution [based on a gaussian random vector] as the number of signals to be summed increases”; [para. 0049] “In the noise generation circuit 5, the independent currents [plurality of samples of artificial nose] ... summed at the node at which ... and a current whose distribution approaches the Gaussian distribution [based on a gaussian random vector] ... random noise... is generated [generating the plurality of samples of artificial noise]”; [para. 0052] “as the number of current sources 131 to 13N increases, [generating the plurality of samples of artificial noise] a noise current that approaches the Gaussian distribution (i.e., a more random noise current) [based on a gaussian random vector] can be generated”) a selection matrix, and a signal constraint parameter. ([para. 0046] “The switch 12n [generating the plurality of samples of artificial noise – see Fig. 1] ... is turned on or off according to [based on] ... the oscillator 10n [a selection matrix] .... the current source 13n [a signal constraint parameter]”; [para. 0069] “oscillators 101 to 10N to the number indicated by the control signal from the control circuit 14 [a selection matrix]”; [para. 0053] “as the number N of current sources ... increases, the current consumption of the overall IC chip [signal constraint parameter] also increases”)
Arisawa does not clearly teach wherein the at least one power constraint parameter comprises the signal constraint parameter and a rank parameter, and wherein the selection matrix comprises a diagonal matrix having a rank less than the rank parameter.
However, Miller teaches wherein the at least one power constraint parameter comprises the signal constraint parameter ([Miller, para. 0025] “the CPU may be operated to draw an increased amount of power [the at least one power constraint parameter] from the switched mode power supply to cause the change in the noise signal [comprises the signal constraint parameter] generated by the switched mode power supply ... this change in the amount of current ... causes the switched mode power supply to output a changed frequency [signal constraint parameter] of the noise signal”) and a rank parameter. ([Para. 0050] “listening over power line [the power constraint parameter as the CPU is operated to control the power as per Miller above] ... to identify the standard noise output of each computing system ... within two or three standard deviations [rank parameter] from the mean noise output by a computing system”)
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to have modified the elements disclosed by Arisawa in view of El-Alfy with the teachings of Miller to include wherein the at least one power constraint parameter comprises the signal constraint parameter and a rank parameter. One of ordinary skill in the art would have been motivated to make this modification because as a result, there is less likelihood that the transmission of the noise signal will be detected by a third party. (Miller, para. 0041)
Arisawa in view of El-Alfy and further in view of Miller does not clearly teach wherein the selection matrix comprises a diagonal matrix having a rank less than the rank parameter.
However, Shvetsov teaches wherein the selection matrix comprises a diagonal matrix having a rank ([Shvetsov, para. 0063] “event selection module ... to perform a singular decomposition ... SVD ... of the obtained matrix M [selection matrix] into [comprises] ... D ... a diagonal matrix ... Singular numbers [a rank] are the diagonal elements of the diagonal matrix”) having a rank less than the rank parameter. ([Para. 0160] “event ... is classified as undesirable ... if the measure of central tendency of the rating values ... of all events [a rank] .... is less than a predetermined value [the rank parameter]”)
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to have modified the elements disclosed by Arisawa in view of El-Alfy and further in view of Miller with the teachings of Shvetsov to include wherein the selection matrix comprises a diagonal matrix having a rank less than the rank parameter. One of ordinary skill in the art would have been motivated to make this modification because the SVD is the best known and widely used factoring method. (Shvetsov, para. 0063)
As per claim 3, Arisawa in view of El-Alfy and further in view of Shvetsov and in view of Shvetsov teaches claim 2.
Arisawa in view of El-Alfy and Shvetsov does not clearly teach wherein the signal constraint parameter comprises a direct current (DC) component and an alternating current (AC) component.
However, Miller teaches wherein the signal constraint parameter comprises a direct current (DC) component and an alternating current (AC) component. ([Miller, para. 0002] “switched mode power supply includes circuitry configured to receive input power and to convert the input power to a desired output power [signal constraint parameter as per above] ... convert alternating current (AC) power to direct current (DC) power, DC power to AC power, AC power to AC power, or DC power to DC power [comprises a direct current (DC) component and an alternating current (AC) component]”)
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Arisawa, El-Alfy, Miller and Shvetsov for the same reasons as disclosed above.
As per claim 12, the claim language is identical or substantially similar to that of claim 2. Therefore, it is rejected under the same rationale applied to claim 2.
As per claim 13, the claim language is identical or substantially similar to that of claim 3. Therefore, it is rejected under the same rationale applied to claim 3.
Claims 5 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Arisawa in view El-Alfy as applied to claim 1 above, and further in view of Pratt et al. (US Pub. 2016/0219506) (hereinafter “Pratt”)
As per claim 5, Arisawa in view El-Alfy teaches claim 1.
Arisawa also teaches wherein the side channel signal comprises a signal on a side channel, ([Arisawa, para. 0050] “Therefore, the current I that can be observed outside the IC chip [side channel signal] ... based on ... current Ides [signal on a side channel]”) wherein overlaying each respective sample of artificial noise comprises reducing the channel capacity by reducing the SNR. ([Para. 0050-0051] “a current I flowing in the power supply line L is obtained by superimposing [overlaying] the noise current In generated by the noise generation circuit 5 [each respective sample of artificial noise] on the current Ides [signal] consumed by the encryption processing circuit 1 ... The noise current In is superimposed on the consumed current Ides to hide the consumed current Ides from outside the IC chip [reducing the SNR], and is therefore desirably random ... the randomness is high [the BRI of reducing the channel capacity as randomness is opposite of information/capacity in view of para. 0104-0105 of the instant application]”)
Arisawa in view of El-Alfy does not clearly teach the side channel having a channel capacity that is logarithmically proportional to a signal to noise ratio (SNR) of the side channel, the SNR being inversely proportional to each respective sample of artificial noise.
However, Pratt teaches the side channel having a channel capacity that is logarithmically proportional to a signal to noise ratio (SNR) of the side channel, the SNR being inversely proportional to each respective sample of artificial noise. ([Pratt, para. 0058] “The information theoretic (IT) transmit EE metric of a band-limited communications system [channel capacity] ... modeled as ...
=
h
F
2
S
N
R
r
N
0
log
2
1
+
S
N
R
r
... Bw is the 3-dB noise bandwidth in Hertz, No is the power spectral density of the noise in units of watts per Hertz [each respective sample of artificial noise] SNR1=PR/(BwNo”)
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to have modified the elements disclosed by Arisawa in view of El-Alfy with the teachings of Pratt to include the side channel having a channel capacity that is logarithmically proportional to a signal to noise ratio (SNR) of the side channel, the SNR being inversely proportional to each respective sample of artificial noise. One of ordinary skill in the art would have been motivated to make this modification because the analytical framework employed to study energy-efficient communications can be applied in the design of energy-efficient architectures and algorithms to provide a gain in network performance. (Pratt, para. 0231)
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Al Faruque et al. (US Pub. 2019/0230113) discloses the SNR being inversely proportional to each respective sample of artificial noise.
Pepin et al. (US Pub. 2015/0222423) discloses superimposing noise over current to make side channel more difficult.
Bolotov et al. (US Pub. 2021/0312045) disclose mitigation of side channel attacks where a plurality of crypto functional units perform cryptographic algorithms and jammer circuitry generates noise to protect from side channel attacks
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZHE LIU whose telephone number is (571) 272-3634. The examiner can normally be reached on Monday - Friday: 8:30 AM to 5:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Carl Colin can be reached on (571) 272-3862. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see https://ppair-my.uspto.gov/pair/PrivatePair. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at (866) 217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call (800) 786-9199 (IN USA OR CANADA) or (571) 272-1000.
/ZHE LIU/Examiner, Art Unit 2493
Prosecution Insights