Prosecution Insights
Last updated: August 16, 2026
Application No. 18/833,581

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE

Non-Final OA §102
Filed
Jul 26, 2024
Priority
Feb 17, 2022 — JP 2022-022886 +1 more
Examiner
SENGDARA, VONGSAVANH
Art Unit
Tech Center
Assignee
Semiconductor Energy Laboratory Co., Ltd.
OA Round
1 (Non-Final)
72%
Grant Probability
Favorable
1-2
OA Rounds
1y 2m
Est. Remaining
90%
With Interview

Examiner Intelligence

Grants 72% — above average
72%
Career Allowance Rate
673 granted / 935 resolved
+12.0% vs TC avg
Strong +18% interview lift
Without
With
+18.5%
Interview Lift
resolved cases with interview
Typical timeline
3y 3m
Avg Prosecution
62 currently pending
Career history
1012
Total Applications
across all art units

Statute-Specific Performance

§101
2.2%
-37.8% vs TC avg
§103
51.6%
+11.6% vs TC avg
§102
27.1%
-12.9% vs TC avg
§112
18.2%
-21.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 935 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-3, 7-11 and 13-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sasaki 20160233251. PNG media_image1.png 618 1229 media_image1.png Greyscale Regarding claim 1, fig. 3 of Sasaki discloses a semiconductor device comprising: a semiconductor layer 140, a first conductive layer 120, a second conductive layer, a third conductive layer, a first insulating layer, and a second insulating layer, wherein the first insulating layer 130/110 is provided over the first conductive layer 120, wherein the first insulating layer has a first opening 131 reaching the first conductive layer, wherein the semiconductor layer 140 is in contact with a top surface and a side surface of the first insulating layer and a top surface of the first conductive layer, wherein the second conductive layer 145 is provided over (the side in region 132) the semiconductor layer, wherein the second conductive layer 145 has a second opening in a region 132 overlapping with the first opening, wherein the second insulating layer 150 (gate insulating layer which portion of 50 under the gate electrode 160) is provided over the semiconductor layer 140 and the second conductive layer 145, wherein the third conductive layer 160 is provided over the second insulating layer, and wherein the first insulating layer has a stacked-layer structure of a third insulating layer and a fourth insulating layer over the third insulating layer (as labeled by examiner above). Regarding claim 11, Sasaki discloses a method for manufacturing a semiconductor device, comprising: forming a first conductive film; processing the first conductive film to form a first conductive layer (fig. 5 and par [0081]); forming a first insulating film 130 (fig. 7) over the first conductive layer; processing the first insulating film to form a first insulating layer having a first opening reaching the first conductive layer (fig. 7); forming a semiconductor layer in contact with a top surface of the first conductive layer and a top surface and a side surface of the first insulating layer (fig. 9); forming a second conductive film 145 over the semiconductor layer (fig. 9 showing 145 over the side surface of 140); processing the second conductive film to form a second conductive layer having a second opening in a region overlapping with the first opening (fig. 7); forming a second insulating layer 150 (fig. 10) over the semiconductor layer and the second conductive layer; and forming a third conductive layer 160 over the second insulating layer, and PNG media_image2.png 633 1090 media_image2.png Greyscale wherein the first insulating layer has a stacked-layer structure of a third insulating layer and a fourth insulating layer over the third insulating layer. Regarding claim 2, fig. 3 of Sasaki discloses wherein the first insulating layer comprises a fifth insulating layer 110 (par [0055] - aluminum nitride oxide (AlN.sub.xO.sub.y)), wherein the fifth insulating layer is positioned between the third insulating layer and the first conductive layer, and wherein the fifth insulating layer comprises a region having a film density higher than a film density of the third insulating layer ( SiO.sub.x par [0061]). Regarding claim 3, fig. 3 of Sasaki discloses wherein the first insulating layer comprises a fifth insulating layer 110 (par [0055] - aluminum nitride oxide (AlN.sub.xO.sub.y)), wherein the fifth insulating layer is positioned between the third insulating layer ( SiO.sub.x par [0061]) and the first conductive layer, and wherein the fifth insulating layer comprises a region having a content of nitrogen higher than a content of nitrogen of the third insulating layer. Regarding claim 7, par [0058] of Sasaki discloses wherein a thickness of the first insulating layer is greater than or equal to 0.01 μm and less than 3 μm ([0058] The underlying layer 110 described above may be formed of a thin film, the thickness of which is controllable by a nanometer order (range less than 1 μm)). Regarding claim 8, Sasaki discloses wherein the first conductive layer comprises an oxide conductor (par [0059] - electrode 120 may be formed of a conductive oxide such as ITO (indium tin oxide). Regarding claims 9-10, par [0064] of Sasaki disclose wherein the second conductive layer comprises an oxide conductor (ITO (indium tin oxide)). Regarding claims 13 and 15, fig. 3 of Sasaki (as labeled by examiner above) discloses wherein the fourth insulating layer comprises a region having (150 above 139 region) a film density higher (AlO.sub.x, AlN.sub.x, AlO.sub.xN.sub.y, AlN.sub.xO.sub.y) than a film density of the third insulating layer ( SiO.sub.x par [0061]). Regarding claims 14 and 16, Sasaki discloses wherein the fourth insulating layer comprises a region (150 above 139 region) having a content of nitrogen higher higher (AlO.sub.x, AlN.sub.x, AlO.sub.xN.sub.y, AlN.sub.xO.sub.y) than a content of nitrogen of the third insulating layer ( SiO.sub.x par [0061]). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to VONGSAVANH SENGDARA whose telephone number is (571)270-5770. The examiner can normally be reached 9AM-6PM EST Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached on (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /VONGSAVANH SENGDARA/Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Jul 26, 2024
Application Filed
Jul 23, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
72%
Grant Probability
90%
With Interview (+18.5%)
3y 3m (~1y 2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 935 resolved cases by this examiner. Grant probability derived from career allowance rate.

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