DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to application filed on 07/29/2024.
Currently claims 11-22 are pending in the application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/29/2024 was filed before the mailing date of the office action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement was considered by the examiner.
Claim Rejections - 35 USC § 112 (b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 11-22 are rejected under 35 U.S.C. 112 (b), as being indefinite for failing to particularly pointing out and distinctly claim the subject matter which the inventor or a joint inventor, regard as their invention.
Regarding claim 11, the claim recites “a first region and a second region disposed on and below the first region” (claim 11, lines 1–2). It is unclear how a single “second region” can be disposed both “on” and “below” the first region at the same time. The metes and bounds of the spatial relationship between the first and second regions cannot be determined. Clarification is required (e.g., “a second region disposed below the first region,” consistent with the specification). For purposes of examination, the second region is treated as being disposed adjacent to (including below) the first region.
Regarding claim 13, the claim recites “between the reinforcing pattern parts and the second pattern parts” (claim 13). There is insufficient antecedent basis for “the reinforcing pattern parts,” because parent claim 11 introduced only a single “a reinforcing pattern part,” and for “the second pattern parts,” because claim 13 earlier introduced only “a second pattern part” (singular). It is unclear whether one or a plurality of these parts is intended. Clarification and/or correction is required.
Regarding claims 14 and 15, each claim refers back to “the first pattern part” and “the second pattern part” (singular), whereas claim 11 introduced “a plurality of first pattern parts.” There is insufficient antecedent basis and it is unclear which one of the plurality of first pattern parts is referenced. For purposes of examination, the limitations are read as directed to any one of the plurality of first pattern parts.
Regarding claims 16 and 17, each claim recites that each first pattern part has a ring shape “surrounding the hole” / an opening portion “overlapping the hole” (singular), whereas the claim earlier introduced “a plurality of holes.” There is insufficient antecedent basis for “the hole.” Clarification is required (e.g., “a corresponding one of the plurality of holes”).
Regarding claim 20, the claim recites a circuit pattern “disposed on the first surface” of the substrate and further recites that “the second pattern region is non-overlapping with the substrate in the thickness direction.” These recitations are contradictory: it is unclear how a pattern region that is disposed on the substrate’s first surface can simultaneously be non-overlapping with the substrate in the thickness direction. Clarification is required. For purposes of examination the examiner interprets the second pattern region as lying over a region of the first surface that is free of the underlying insulating base, consistent with the specification.
Regarding claim 21, the claim recites “a first metal layer and a second metal layer disposed on the second metal layer” (claim 21, lines 1–2). A layer cannot be disposed on itself; the limitation is internally inconsistent and renders the claim indefinite. Based on the specification, the limitation is understood to intend “a second metal layer disposed on the first metal layer,” and is examined accordingly. Correction is required.
Claims 12, 18-19 and 22 are also rejected due to their dependence on a rejected base claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over US 2014/0240949 A1 (Kim) in view of US 2003/0172526 A1 (Komatsubara).
Regarding claim 11, Kim discloses, a smart IC substrate module (a substrate strip for mounting semiconductor chips; Fig. 1; [0039] – [0048]) comprising:
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a substrate (100 and 200) including a first region and a second region (substrate region 100 and dummy region 200; Fig. 1; [0037], [0040]);
a circuit layer disposed in the first region (110; substrate units carrying circuit patterns in the substrate region; Fig. 1; [0039], [0042]);
a conductive layer (210 / 211; metal patterns / first metal patterns; Fig. 1; [0042], [0045]–[0046]) disposed in the second region (dummy region 200) and comprising a plurality of first pattern parts spaced apart from each other in a first (longitudinal) direction (metal patterns / first metal patterns arranged at predetermined intervals in the longitudinal direction);
a reinforcing pattern part (220; rib patterns) extending in the first direction (longitudinal) between the plurality of first pattern parts and directly connecting them in the first direction (rib patterns formed between and connecting the metal patterns to one another; FIG. 1; [0042], [0048]–[0049]).
But Kim fails to teach explicitly that (i) metal patterns 210 are described as dummy patterns provided in the dummy region for warpage control and are not expressly recited as being electrically connected to, and disposed continuously into, the circuit layer of the first region; and (ii) Kim illustrates the first pattern parts as solid circular/polygonal patterns rather than expressly “ring”-shaped patterns.
However, in analogous art, Komatsubara teaches, forming a continuous conductive layer (3 conductive layer) over the entire surface that underlies and joins both a circuit pattern (6) and a neighboring dummy pattern (7) (conductive layer 3 formed on the entire one surface of the substrate; Figs. 2, 5; [0047]–[0049]) and
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Komatsubara further teaches a dummy pattern (7) arranged so as to surround a circuit pattern (dummy pattern surrounding the circuit pattern; Fig. 9(b); [0007], [0072] – [0074]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Kim and Komatsubara before them, to form Kim’s conductive metal/rib patterns as a conductive layer extending from the dummy (second) region into and electrically connected with the circuit layer of the substrate (first) region, and to configure the first pattern parts in a ring/surrounding shape as taught by Komatsubara, and provide a uniform plating-current path and thereby suppress localized overcurrent, resistance increase, and plating non-uniformity. Configuring a solid pattern as a ring is further a mere change in shape that would have been obvious absent a showing of criticality (MPEP 2144.04(IV)(B)).
Regarding claim 12, Kim teaches that the metal patterns (210) and the rib patterns (220) occupy 50% to 70% of the entire area of the dummy region (FIG. 1; [0056] – [0058]). Kim thus recognizes the areal coverage of the conductive pattern within the second region as a result-effective variable that governs surface flatness and plating/molding uniformity. It would have been obvious to one of ordinary skill in the art to optimize that coverage, including to a value of 20% to 30% of the total area of the second region as claimed, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges of a result-effective variable involves only routine skill in the art (MPEP 2144.05(II)). Absent a showing that the claimed 20–30% range achieves an unexpected result relative to Kim’s disclosed range, the claimed range is prima facie obvious.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over US 2003/0172526 A1 (Komatsubara).
Regarding claim 20, Komatsubara discloses, a smart IC substrate comprising:
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a substrate (1) including a first surface (1A) and a second surface (1B) opposite to the first surface (1A) (Figs. 1, 5 and 6; [0038]–[0039]);
a circuit pattern (circuit pattern and dummy pattern; 6 and 7; Figs. 4, 5; [0051]) disposed on the first surface (1A);
wherein the circuit pattern (6 and 7) includes a first pattern region (6) and a second pattern region (7), the first pattern region (6) overlapping the substrate/insulating base (1 and 2) in the thickness direction (Fig. 5; [0060]–[0061]);
the second pattern region (7; dummy pattern; Fig. 5; [0060]–[0061]) being non-overlapping with the insulating base (2) in the thickness direction;
wherein a thickness of the first pattern region (6) is greater than that of the second pattern region (7) (thickness of circuit pattern 6 = 2–30 µm; 6; Fig. 8; [0056]–[0061]; Komatsubara expressly teaches that the circuit pattern 6 (formed over the insulating layer 2) and the dummy pattern 7 (in the area free of the insulating layer) differ in thickness owing to differing plating current density [0005]). In MPEP 2143 (I) (E), it is stated that it is "Obvious to try" – choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success.
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Komatsubara and MPEP 2143 (I) (E) before him/her, to modify the teachings of a smart IC substrate and make the first pattern region greater than that of the second pattern region.
Claims 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over US 2003/0172526 A1 (Komatsubara) and further in view of US 2006/0070769 A1 (Kim2).
Regarding claim 21, Komatsubara discloses, the smart IC substrate of claim 20, wherein the first pattern region (6) includes a conductive seed/base layer with the wiring metal (3) formed thereon, and that the second (dummy) pattern region (7) includes the same base layer (Fig. 5; [0060] – [0064]);
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second pattern region including the first metal layer (dummy pattern 7 formed on the same conductive layer 3; Fig. 5; [0060] – [0064]).
But Komatsubara fails to teach explicitly, the first pattern region includes a first metal layer and a second metal layer disposed on the second metal layer,
However, in analogous art, Kim2 teaches, a circuit pattern formed of a first electroless plating layer (131, left side; Fig. 1e-1g; [0012]), a second electroless plating layer (131, right side; Fig. 1e-1g; [0012]), and an electrolytic plating layer (141/142; Figs. 1e-1g; [0013] – [0015]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Komatsubara and Kim2 before them, to form Komatsubara’s circuit pattern and modify it with Kim2’s first-metal-layer/second-metal-layer plated construction in order to achieve reliable inter-layer connection and controlled edge profile of the circuit pattern ([0009]–[0015]). Absent this important teaching in Komatsubara, a person with ordinary skill in the art would be motivated to reach out to Kim2 while forming a circuit pattern of Komatsubara.
Regarding claim 22, the combination of Komatsubara and Kim2 teaches, the smart IC substrate of claim 20, wherein the plurality of spaced-apart circuit patterns and at least one connection pattern connected thereto (circuit pattern 6 and connecting conductor; Fig. 8; [0071] – [0072]; Komatsubara Ref.). Neither reference is limited to a particular connection-pattern width; however, selecting a line width of 0.1 mm to 0.5 mm for the connection pattern would have been an obvious matter of routine optimization of a result-effective variable (line width governing current density and resistance) absent a showing of criticality (MPEP 2144.05(II)).
Allowable Subject Matter
Claims 13-19 are objected to as being dependent upon rejected base claims, but would be allowable if rewritten in independent forms including all of the limitations of the base claims and any intervening claims.
Regarding claim 13, the closest prior art, US 2014/0240949 A1 (Kim), in conjunction with US 2003/0172526 A1 (Komatsubara) and US 2006/0070769 A1 (Kim2), and in combination with the other claimed features, fails to disclose, “the specific multi-part conductive routing recited, namely a first connection pattern part positioned farther from the first region than the first pattern parts, a second pattern part spaced apart from the first pattern parts in a second direction and extending in the first direction, a second connection pattern part connecting the first pattern parts and the reinforcing pattern part to the second pattern part, a third pattern part extending in the second direction from the second pattern part and disposed closer to the first region than the second pattern part, and a fourth pattern part extending from the third pattern part in the first direction. Kim discloses only metal patterns joined by rib patterns within the dummy region and does not disclose this hierarchical connection/routing structure, which the specification describes as material to establishing a balanced, low-overcurrent current path ([0063], [0078], [0081]).
Claims 14–19 are also allowable due to their dependence on an allowable base claim subject to correction of the § 112(b) issues noted above.
Examiner’s Note (Additional Prior Arts)
The examiner included a few prior arts which were not used in the rejection but are relevant to the disclosure.
US 2016/0181195 A1 (Kim) - A substrate includes a substrate body including a plurality of chip mounting regions and a peripheral region surrounding the plurality of chip mounting regions, each of the chip mounting regions including a conductive plane. The substrate further includes a conductive support structure located in the peripheral region, first conductive lines connected between the conductive planes of adjacent chip mounting regions, and second conductive lines connected between the conductive support structure and the conductive planes of chip mounting regions located adjacent the peripheral region.
US 2022/0129657 A1 (Lim) - A fingerprint sensor package is disclosed including a package substrate including an upper surface in which a sensing region and a peripheral region surrounding the sensing region are defined, and a lower surface facing the upper surface; a plurality of first sensing patterns located are arranged in the sensing region, are apart from each other in a first direction, and extend in a second direction crossing the first direction; a plurality of second sensing patterns that are arranged in the sensing region, are apart from each other in the second direction, and extend in the first direction; a coating member covering the sensing region; an upper ground pattern in the peripheral region and apart from the coating member to surround the coating member in the first and second directions; and a controller chip on the lower surface of the package substrate; and a plurality of capacitors.
US 2021/0045229 A1 (Lim) - A flexible circuit board is disclosed including a substrate, a conductive pattern part disposed on the substrate; and a protective layer partially disposed on the conductive pattern part, wherein the conductive pattern part includes a first conductive pattern part and a second conductive pattern part which are spaced apart from each other, each of the first conductive pattern part and the second conductive pattern part includes a wiring pattern layer, a first plating layer, and a second plating layer that are sequentially placed on the substrate, the first conductive pattern part includes a first open region in which the protective layer is open, the second conductive pattern part includes a second open region in which the protective layer is open, and a content of tin of the second plating layer in the first open region is greater than that of the second plating layer in the second open region.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to S M SOHEL IMTIAZ whose telephone number is (408) 918-7566. The examiner can normally be reached on 8AM-5PM, M-F, PST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/S M SOHEL IMTIAZ/Primary Patent Examiner
Art Unit 2812
07/25/2026
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