DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
1. Acknowledgement is made of the preliminary amendment received on 8/29/2024. Claims 1-20 are pending in this application. Claims 19-20 are new.
Drawings
2. The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: ref. number 70 (Fig. 4). Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
3. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Appropriate correction is required.
Claim Objections
4. The claims are objected because of the following reasons:
Re claim 1, line 11:
-in front of “light emitting”, delete “The” and insert --the--,
-after “emitting”, delete “device” and insert --devices--.
Re claim 18, line 12:
-in front of “light emitting”, delete “The” and insert --the--,
-after “emitting”, delete “device” and insert --devices--.
Re claim 20, page 8, line 2:
-in front of “light emitting”, delete “The” and insert --the--,
-after “emitting”, delete “device” and insert --devices--.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claims 1-7, 9, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Dong et al. (US 2022/0375966).
Re claims 1 & 18, Dong teaches, under BRI, Figs. 1-2, [0079, 0090, 0117, 0119, 0153], a display device, comprising a display panel, and the display panel comprising:
-an underlay substrate (110);
-a driver circuit layer (130) disposed on a side of the underlay substrate (1140), wherein the driver circuit layer comprises a plurality of transistors (210);
-a resistance reduction layer (390) disposed on a side of the driver circuit layer (130) away from the underlay substrate (110), wherein the resistance reduction layer (390) comprises a plurality of resistance reduction patterns (391, 501, 502), each of the resistance reduction patterns comprises a first electrode (391, a second electrode (501), and a first power line (502), the first electrode (391) and the first power line (502) are electrically connected to the transistors (210); and
-light emitting devices (141) disposed on a side of the resistance reduction layer (390) away from the underlay substrate (110), wherein each of the light emitting device comprises a first electrode member (142) and a second electrode member (142), the first electrode member (391) is bonded to the first electrode (142), and the second electrode member (501) is bonded to the second electrode (142).
PNG
media_image1.png
341
539
media_image1.png
Greyscale
Dong does not explicitly teach wherein a voltage uniformity on the first power line is greater than 85%.
Dong does teach “thickness of the electrode layer 390 is greater than 1 μm, the square resistance of the electrode layer 390 is small, so that the voltage drop on the power supply lead 502 can be reduced” [0119].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ/modify the teaching as taught by Dong to obtain a voltage uniformity on the first power line is greater than 85% as claimed, because it aids in improving the ability of the driving transistors & display quality.
Further, it would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose particular voltage uniformity, because applicant has not disclosed that, in view of the applied prior art, the voltage uniformity is for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. For that matter, applicant has not disclosed that the voltage uniformity is for any purpose or produce any result. Moreover, it appears prima facie that the process would possess utility using another voltage uniformity. Indeed, it has been held that mere voltage uniformity limitation(s) is prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Furthermore, it would have been obvious to try the particular claimed voltage uniformity, because a change in voltage uniformity would have been a known option within the technical grasp of a person of ordinary skill in the art and, "a person of ordinary skill in the art has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense." KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (U.S. 2007). See also, Pfizer Inc. v. Apotex Inc., 82 USPQ2d 1852 (Fed. Cir. 2007).
Re claims 2 & 19, Dong teaches, under BRI, Figs. 1-2, wherein the resistance reduction pattern further comprises a second power line (e.g. connected to 2nd transistor, Fig. 1) disposed opposite to and spaced from the first power line (502), a voltage uniformity of the second power line is greater than 85% (see discussed above in claim 1), and the second power line and the second electrode (501) are disposed integrally (within device structure).
Re claim 3, Dong teaches, [0119, 0124, 0125], wherein material of the resistance reduction layer (390) comprises copper, and a thickness of the resistance reduction layer ranges from 2 microns to 15 microns (greater than 1 um).
Re claim 4, Dong teaches, Fig. 2, [0124, 0125], wherein the resistance reduction layer comprises a first copper layer (411) and a second copper layer (412), the second copper layer (412) is located on a side of the first copper layer (411) away from the driver circuit layer (130), and a thickness of the second copper layer (412) (from surface of 411) is greater than a thickness of the first copper layer (411) (from surface of 601).
Re claim 5, Dong teaches, Fig.2, wherein a boundary of the second copper layer (412) extends beyond a boundary of the first copper layer (411).
Re claim 6, Dong teaches, Fig. 2, [0127], wherein a first planarization layer (601) located between the driver circuit layer (130) and the resistance reduction layer (390); and wherein a first via hole (filled with 411) is defined in the first planarization layer (601), and the first electrode (391) is connected to the transistor (210).
Re claim 7, Dong teaches, Figs. 1-2, [0106, 0117], a first planarization layer (380) disposed between the driver circuit layer (130) and the resistance reduction layer (390); a first metal layer (370) disposed on a side of the first planarization layer (380) away from the resistance reduction layer (390), wherein the first metal layer (370) comprises an auxiliary electrode, and the first electrode (391) is connected to the auxiliary electrode through a second via hole in the first planarization layer (380); and a second planarization layer (360) disposed on a side of the first metal layer (370) away from the resistance reduction layer (390), wherein the auxiliary electrode is connected to the transistor (210) through a third via hole in the second planarization layer (360).
Re claim 9, Dong teaches, Fig. 2, [0119, 0128], wherein a first gap (e.g., between 502, 391) is formed between adjacent ones of the resistance reduction patterns (391, 501, 502), the display panel further comprises a filling structure (602) disposed in the first gap, and along a direction perpendicular to the underlay substrate (110), an absolute value of a difference between a thickness (e.g., 100-200 nm) of the filling structure (602) and a thickness (e.g., greater than 1 um, consider value around 1.5 um) of the resistance reduction pattern (of 390) is less than or equal to 1.5 microns.
Re claim 20, Dong teaches, under BRI, Figs. 1-2, [0079, 0090, 0106, 0117, 0119, 0153], a display device, comprising a display panel, and the display panel comprising:
-an underlay substrate (110);
-a driver circuit layer (130) disposed on a side of the underlay substrate (1140), wherein the driver circuit layer comprises a plurality of transistors (210);
-a resistance reduction layer (390) disposed on a side of the driver circuit layer (130) away from the underlay substrate (110), wherein the resistance reduction layer (390) comprises a plurality of resistance reduction patterns (391, 501, 502), each of the resistance reduction patterns comprises a first electrode (391, a second electrode (501), and a first power line (502), the first electrode (391) and the first power line (502) are electrically connected to the transistors (210); and
-light emitting devices (141) disposed on a side of the resistance reduction layer (390) away from the underlay substrate (110), wherein each of the light emitting device comprises a first electrode member (142) and a second electrode member (142), the first electrode member (391) is bonded to the first electrode (142), and the second electrode member (501) is bonded to the second electrode (142);
wherein the resistance reduction pattern further comprises a second power line (connect to 2nd transistor, Fig. 1) disposed opposite to and spaced from the first power line, and the second power line and the second electrode (501) are disposed integrally (within formed structure);
wherein the display panel further comprises: a first planarization layer (380) disposed between the driver circuit layer (130) and the resistance reduction layer (390);
a first metal layer (370) disposed on a side of the first planarization layer (380) away from the resistance reduction layer (390), wherein the first metal layer (370) comprises an auxiliary electrode, and the first electrode (391) is connected to the auxiliary electrode through a second via hole in the first planarization layer (380); and
a second planarization layer (360) disposed on a side of the first metal layer (370) away from the resistance reduction layer (390), wherein the auxiliary electrode is connected to the transistor (210) through a third via hole in the second planarization layer (360).
PNG
media_image1.png
341
539
media_image1.png
Greyscale
Dong does not explicitly teach wherein a voltage uniformity on the first power line is greater than 85% & a voltage uniformity of the second power line is greater than 85%.
Dong does teach “thickness of the electrode layer 390 is greater than 1 μm, the square resistance of the electrode layer 390 is small, so that the voltage drop on the power supply lead 502 can be reduced” [0119].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ/modify the teaching as taught by Dong to obtain a voltage uniformity on the first/second power lines greater than 85% as claimed, because it aids in improving the ability of the driving transistors & display quality.
Further, it would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose particular voltage uniformity, because applicant has not disclosed that, in view of the applied prior art, the voltage uniformity is for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. For that matter, applicant has not disclosed that the voltage uniformity is for any purpose or produce any result. Moreover, it appears prima facie that the process would possess utility using another voltage uniformity. Indeed, it has been held that mere voltage uniformity limitation(s) is prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Furthermore, it would have been obvious to try the particular claimed voltage uniformity, because a change in voltage uniformity would have been a known option within the technical grasp of a person of ordinary skill in the art and, "a person of ordinary skill in the art has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense." KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (U.S. 2007). See also, Pfizer Inc. v. Apotex Inc., 82 USPQ2d 1852 (Fed. Cir. 2007).
6. Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Dong in view of Imazeki et al. (US 2023/0420626).
The teachings of Dong have been discussed above.
Re claim 8, Dong does not explicitly teach a soldering layer, the first electrode member and the second electrode member are bonded to the first electrode and the second electrode respectively through corresponding portions of the soldering layer, and the first electrode and the second electrode contact the soldering layer.
Imazeki teaches, Fig. 4, [0074], a soldering layer (solder film), the first electrode member (20EA) and the second electrode member (20EK) are bonded to the first electrode and the second electrode (33) respectively through corresponding portions of the soldering layer (solder film), and the first electrode and the second electrode (33) contact the soldering layer (solder film).
As taught by Imazeki, one of ordinary skill in the art would utilize & modify the above teaching to obtain a soldering film between electrodes and electrodes members as claimed, because it aids in improving mechanical bonding between components and stability of the formed structure.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Imazeki in combination Dong due to above reason.
Allowable Subject Matter
7. Claims 10-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
8. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY T.V. NGUYEN whose telephone number is (571)270-7431. The examiner can normally be reached Monday-Friday, 7AM-4PM, alternative Friday off.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, EVA MONTALVO can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 7/15/26
Prosecution Insights