Prosecution Insights
Last updated: October 02, 2026
Application No. 18/834,335

SEMICONDUCTOR DEVICE

Non-Final OA §102
Filed
Jul 30, 2024
Priority
Mar 02, 2022 — nonprovisional of PCTJP2022008992
Examiner
MUIR, MATTHEW SINCLAIR
Art Unit
Tech Center
Assignee
Hitachi Ltd.
OA Round
1 (Non-Final)
70%
Grant Probability
Favorable
1-2
OA Rounds
5m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 70% — above average
70%
Career Allowance Rate
95 granted / 136 resolved
+9.9% vs TC avg
Strong +30% interview lift
Without
With
+30.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
27 currently pending
Career history
154
Total Applications
across all art units

Statute-Specific Performance

§103
55.7%
+15.7% vs TC avg
§102
26.8%
-13.2% vs TC avg
§112
16.7%
-23.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 136 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1 and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kimura (JP 2009182312 A). As to Claim 1, Kimura discloses: A semiconductor device (device of Fig. 5, some description is same as Figs. 1-3, Par. 0033 “The rest is the same as in Example 1”) comprising: one or more semiconductor modules 2 arranged in a row (semiconductor modules 2 arranged in a row); a pair of cooling members 3 disposed so as to sandwich the one or more semiconductor modules 2 arranged in a row and configured to cool the semiconductor modules 2 (Par. 0015 “The semiconductor cooling structure 1 in this example consists of multiple semiconductor modules 2, each containing a semiconductor element 21, arranged in parallel between a pair of cooling pipes 3 through which a cooling medium flows”); a pair of sandwiching members (pressing plates 41) each disposed on an opposite side of the semiconductor module 2 across a corresponding one of the pair of cooling members 3 to oppose the corresponding one of the pair of cooling members 3 (Par. 0019 “the clamping means 4 consists of a pair of pressing plates 41 arranged on the side of the cooling tube 3 opposite to the semiconductor module 2”); and a coupling portion (bolt 42, nut 43) that couples the pair of sandwiching members 41 to each other and presses each of the pair of sandwiching members 41 against the opposing one of the cooling members 3 (Par. 0019 “the clamping means 4 consists of a pair of pressing plates 41 arranged on the side of the cooling tube 3 opposite to the semiconductor module 2, a plurality of through bolts 42 that pass through the pair of pressing plates 41 at their ends, and nuts 43 that are screwed onto the through bolts 42. The clamping means 4 then presses the pair of cooling pipes 3 against the semiconductor module 2 by tightening the pair of pressing plates 41 in a direction that brings them closer together using the through bolt 42 and nut 43”), wherein at least one of the pair of sandwiching members 41 includes a plurality of support portions (support plate 45) disposed to oppose ends of the one or more semiconductor modules 3 arranged in a row and a space 11 between the semiconductor modules 2 (support plates 45 disposed adjacent opposite ends of semiconductor modules 2 and gaps 11), and a spring portion 44 extending from each of the plurality of support portions 45 in an arrangement direction of the semiconductor modules 2 and abutting the cooling member 3 (spring members extend both vertically and horizontally and indirectly abut 3), and the coupling portion 42,43 couples the support portion 45 provided to the one of the pair of sandwiching members 41 and another sandwiching member 41 (42,43 couples 45 and both pressing plates 41, see Fig. 5). As to Claim 10, Kimura discloses: wherein each of the pair of cooling members 3 includes an opposing portion opposing the semiconductor module 2 (portions of 3 contacting semiconductor modules 2), and a flexible portion 31 provided at two ends of the opposing portion in the arrangement direction (variable portions 31 are in arrangement direction of semiconductor modules 2 and on either side of modules 2; Par. 0035 “The variable portion 31 may be formed on only one of the pair of cooling tubes 3, or on both…the variable part 31 can be made structurally more easily deformable than other parts”). Allowable Subject Matter Claims 2-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: As to claims 2-9, the allowability resides in the overall structure and functionality of the device as recited in the dependent claim 2, including all of the limitations of their base claims and intervening claims, and at least in part, because claim 2 recites the following limitations: “wherein each of the pair of sandwiching members includes a plurality of support portions disposed to oppose ends of the one or more semiconductor modules arranged in a row and a space between the semiconductor modules, and a spring portion extending from each of the plurality of support portions in an arrangement direction of the semiconductor modules and abutting the cooling member, and the coupling portion includes, for each of the support portions, a coupling member that couples the support portions opposing each other of the pair of sandwiching members.” – claim 2. Jaecklin (US 3786168 A) discloses a holder member for a semiconductor element, however does not disclose the claimed details of each of the pair of sandwiching members. Gao (US 11382241 B2) discloses cooling components on either side of a processor and spring used for a proper pressure load, however does not disclose the claimed details of each of the pair of sandwiching members. Asakura (JP 2014013880 A) discloses a semiconductor cooling structure with a leaf spring, however does not disclose the claimed details of each of the pair of sandwiching members. The aforementioned limitations in combination with all remaining limitations of claim 2, are believed to render said claim 2 and all claims dependent therefrom allowable over the prior art of record, taken alone or in combination. Further, Examiner has not identified any double patenting issues. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW S MUIR whose telephone number is (571)270-1329. The examiner can normally be reached Monday - Friday 8 am - 5 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jayprakash Gandhi can be reached at 571-272-3740. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MATTHEW SINCLAIR MUIR/ Examiner, Art Unit 2841 /Jayprakash N Gandhi/ Supervisory Patent Examiner, Art Unit 2841
Read full office action

Prosecution Timeline

Jul 30, 2024
Application Filed
Aug 10, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
70%
Grant Probability
99%
With Interview (+30.4%)
2y 7m (~5m remaining)
Median Time to Grant
Low
PTA Risk
Based on 136 resolved cases by this examiner. Grant probability derived from career allowance rate.

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