Prosecution Insights
Last updated: July 17, 2026
Application No. 18/834,361

USING COUNTER SPACE AND STOP BITS FOR DATA TRANSMISSION

Non-Final OA §103§112
Filed
Jul 30, 2024
Priority
Feb 10, 2022 — nonprovisional of PCTEP2022053268
Examiner
SHAH, SAUMIT
Art Unit
Tech Center
Assignee
Nokia Corporation
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
4m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allowance Rate
475 granted / 542 resolved
+27.6% vs TC avg
Moderate +11% lift
Without
With
+10.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
13 currently pending
Career history
560
Total Applications
across all art units

Statute-Specific Performance

§101
1.8%
-38.2% vs TC avg
§103
85.2%
+45.2% vs TC avg
§102
3.0%
-37.0% vs TC avg
§112
6.7%
-33.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 542 resolved cases

Office Action

§103 §112
DETAILED ACTION This office action is a response to the 371 application entering national stage from PCT/EP2022/053268 filed on 2/10/2022. Claims 1-12, 14-20 and 24 are pending and ready for examination. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Objections Claim 1 is objected to because of the following informalities: Claim 1, line 11: “re-source” should be “resource”. Appropriate correction is required. Claim 2 is objected to because of the following informalities: Claim 2, line 2: “con-figuration” should be “configuration”. Appropriate correction is required. Claim 24 is objected to because of the following informalities: Claim 24, line 8: “re-source” should be “resource”. Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 20 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 20 recites the limitation "…broadcast information defining the start of the counter space" in line 4. There is insufficient antecedent basis for this limitation in the claim. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-2, 11-12 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Gaspar (Waveform Advancements and Synchronization techniques for Generalized Frequency Division Multiplexing, 2016; provided in Applicant’s IDS dated 7/30/2024) in view of Jiang et al. (US 2021/0167891, hereinafter Jiang). Regarding claim 1, Gaspar discloses An apparatus comprising at least one processor; and at least one memory including computer program code, the at least one memory and computer program code being configured to, with the at least one processor, cause the apparatus at least to [Gaspar Figure 1.1 (page 1) discloses a 5G service architecture comprising various network components such as access network cells, cloud computing, mobile broadband, IoT devices, etc. (Gaspar Figure 1, pages 1 and 2). Processor and memory are implicit]: Obtain M binary string values of M binary strings of a predetermined length N, M and N being two non-null positive integers [Gaspar discloses that a binary data vector source may be encoded. The resulting vector d denotes a data block containing N elements. The elements may be decomposed into K subcarriers, each with M sub symbols (i.e. a predetermined length) [Gaspar page 17, second paragraph (lines 11-17)]; Encode STOP bits over respective resource elements of a counter space, wherein the counter space is a portion of a resource grid having a predetermined size in the time domain and in the frequency domain, wherein counter values are associated with respective resource elements of the counter space according to a predetermined rule, and wherein the counter values of the re-source elements over which the STOP bits are encoded correspond to the M binary string values; and transmit the encoded STOP bits [Gaspar discloses a generalized frequency division multiplexing (GFDM) block where multiple sub symbols can be transmitted per subcarrier in a block (Gaspar page 17, first paragraph). GFDM block corresponds to a counter space of portion of a resource grid with time and frequency domain elements. Gaspar Figure 2.6 (page 18) discloses a resource grid of subcarriers and sub symbols with data blocks. Gaspar discloses that the elements dk,m may be encoded which correspond to data transmitted on the particular subcarrier and sub symbol of the GFDM block (Gaspar page 17, second paragraph (lines 11-17)]. Gaspar does not expressly disclose the features of encoding STOP bits and transmitting the encoded STOP bits. However, in the same or similar field of invention, Jiang Figure 11 discloses an example of a device for bit allocation for encoding/decoding which may include a processor; and may be implemented in hardware, software executed by a processor (Jiang Figure 11, paragraphs 0144-0146). Jiang Figure 5 discloses an example of an encoder that supports bit allocation for encoding/decoding where an encoder may receive vector having a plurality of bits (Jiang paragraphs 0117 and 0118). As disclosed in the example of Figure 5, groups (G0, G1…) may depend of length of base sequence; and the information bits (k) (similar to the STOP bits) may be allocated to each group and correspond to the length of each group (Jiang paragraph 0120). This is similar to counter values over which the STOP bits are encoded corresponding to the binary strings. Jiang Figure 16 further discloses a flowchart for the bit allocation for encoding/decoding where the information bits are encoded and transmitted (Jiang Figure 16, steps 1610, 1620; paragraphs 0185, 0187 and 0188). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Gaspar to have the features of encoding STOP bits over respective resource elements of a counter space, wherein the counter space is a portion of a resource grid having a predetermined size in the time domain and in the frequency domain, wherein counter values are associated with respective resource elements of the counter space according to a predetermined rule, and wherein the counter values of the re-source elements over which the STOP bits are encoded correspond to the M binary string values; and transmitting the encoded STOP bit; as taught by Jiang. The suggestion/motivation would have been to provide improved coding performance and reduce storage and/or computations (Jiang paragraph 0119). Regarding claim 2, Gaspar and Jiang disclose the apparatus of claim 1. Gaspar and Jiang further disclose wherein the counter space is pre-allocated to the apparatus, or configured to the apparatus via one or more con-figuration messages, or broadcast or scheduled for the apparatus for transmission [Jiang Figure 5 discloses an example of an encoder that supports bit allocation for encoding/decoding where an encoder may receive vector having a plurality of bits (Jiang paragraphs 0117 and 0118). As disclosed in the example of Figure 5, groups (G0, G1…) may depend of length of base sequence (Jiang paragraph 0120). Jiang Figure 16 further discloses a flowchart for the bit allocation for encoding/decoding where the information bits are encoded and transmitted (Jiang Figure 16, steps 1610, 1620; paragraphs 0185, 0187 and 0188). This indicates that the counter space is pre-allocated and scheduled for transmission]. In addition, the same motivation is used as the rejection of claim 1. Regarding claim 11, Gaspar and Jiang disclose the apparatus of claim 1. Gaspar and Jiang further disclose wherein the at least one memory and computer program code are configured to, with the at least one processor, cause the apparatus further at least to perform repetition coding on the STOP bits [Jiang discloses that the techniques may facilitate code design by incorporating repetition in the information bit allocation (Jiang paragraph 0119). Further, polarization may be used to create channels via repetition (Jiang paragraphs 0198-0199); indicating repetition coding on the STOP bits]. In addition, the same motivation is used as the rejection of claim 1. Regarding claim 12, Gaspar discloses an apparatus comprising at least one processor; and at least one memory including computer program code, the at least one memory and computer program code being configured to, with the at least one processor, cause the apparatus at least to [Gaspar Figure 1.1 (page 1) discloses a 5G service architecture comprising various network components such as access network cells, cloud computing, mobile broadband, IoT devices, etc. (Gaspar Figure 1, pages 1 and 2). Processor and memory are implicit]: Receive STOP bits encoded over respective resource elements of a counter space, wherein the counter space is a portion of a resource grid having a predetermined size in the time domain and in the frequency domain, wherein counter values are associated with respective resource elements of the counter space according to a predetermined rule, and wherein the counter values of the resource elements over which the STOP bits are encoded correspond to M binary string values of M binary strings of a predetermined length N, M and N being two non-null positive integers [Gaspar discloses a generalized frequency division multiplexing (GFDM) block where multiple sub symbols can be transmitted per subcarrier in a block (Gaspar page 17, first paragraph). GFDM block corresponds to a counter space of portion of a resource grid with time and frequency domain elements. Gaspar Figure 2.6 (page 18) discloses a resource grid of subcarriers and sub symbols with data blocks. Gaspar discloses that the elements dk,m may be encoded which correspond to data transmitted on the particular subcarrier and sub symbol of the GFDM block (Gaspar page 17, second paragraph (lines 11-17)]. Gaspar does not expressly disclose the features of receiving STOP bits encoded over respective resource elements of a counter space; decoding the M binary string values from the received STOP bits; and obtaining the M binary strings corresponding to the M decoded binary string values. However, in the same or similar field of invention, Jiang Figure 11 discloses an example of a device for bit allocation for encoding/decoding (Jiang Figure 11, paragraphs 0144-0146). Jiang Figure 5 discloses an example of an encoder that supports bit allocation for encoding/decoding where an encoder may receive vector having a plurality of bits (Jiang paragraphs 0117 and 0118). As disclosed in the example of Figure 5, groups (G0, G1…) may depend of length of base sequence; and the information bits (k) (similar to the STOP bits) may be allocated to each group and correspond to the length of each group (Jiang paragraph 0120). This is similar to counter values over which the STOP bits are encoded corresponding to the binary strings. Jiang Figure 17 discloses a flowchart for the bit allocation for encoding/decoding where codeword including information bits are received; a plurality of instances partitioned into a plurality of groups associated with the codeword are identified; and a decoding operation of the codeword is performed to obtain set of information bits (Jiang Figure 17, paragraphs 0189-0193). This is similar to receiving encoded STOP bits, decoding the binary string values from the STOP bits, and obtaining the strings. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Gaspar to have the features of receiving STOP bits encoded over respective resource elements of a counter space, wherein the counter space is a portion of a resource grid having a predetermined size in the time domain and in the frequency domain, wherein counter values are associated with respective resource elements of the counter space according to a predetermined rule, and wherein the counter values of the resource elements over which the STOP bits are encoded correspond to M binary string values of M binary strings of a predetermined length N, M and N being two non-null positive integers; decoding the M binary string values from the received STOP bits; and obtaining the M binary strings corresponding to the M decoded binary string values; as taught by Jiang. The suggestion/motivation would have been to provide improved coding performance and reduce storage and/or computations (Jiang paragraph 0119). Regarding claim 24, Gaspar discloses a method comprising: obtaining M binary string values of M binary strings of a predetermined length N, M and N being two non-null positive integers [Gaspar discloses that a binary data vector source may be encoded. The resulting vector d denotes a data block containing N elements. The elements may be decomposed into K subcarriers, each with M sub symbols (i.e. a predetermined length) [Gaspar page 17, second paragraph (lines 11-17)]; Encoding STOP bits over respective resource elements of a counter space, wherein the counter space is a portion of a resource grid having a predetermined size in the time domain and in the frequency domain, wherein counter values are associated with respective resource elements of the counter space according to a predetermined rule, and wherein the counter values of the re-source elements over which the STOP bits are encoded correspond to the M binary string values; and transmitting the encoded STOP bits [Gaspar discloses a generalized frequency division multiplexing (GFDM) block where multiple sub symbols can be transmitted per subcarrier in a block (Gaspar page 17, first paragraph). GFDM block corresponds to a counter space of portion of a resource grid with time and frequency domain elements. Gaspar Figure 2.6 (page 18) discloses a resource grid of subcarriers and sub symbols with data blocks. Gaspar discloses that the elements dk,m may be encoded which correspond to data transmitted on the particular subcarrier and sub symbol of the GFDM block (Gaspar page 17, second paragraph (lines 11-17)]. Gaspar does not expressly disclose the features of encoding STOP bits and transmitting the encoded STOP bits. However, in the same or similar field of invention, Jiang Figure 11 discloses an example of a device for bit allocation for encoding/decoding which may include a processor; and may be implemented in hardware, software executed by a processor (Jiang Figure 11, paragraphs 0144-0146). Jiang Figure 5 discloses an example of an encoder that supports bit allocation for encoding/decoding where an encoder may receive vector having a plurality of bits (Jiang paragraphs 0117 and 0118). As disclosed in the example of Figure 5, groups (G0, G1…) may depend of length of base sequence; and the information bits (k) (similar to the STOP bits) may be allocated to each group and correspond to the length of each group (Jiang paragraph 0120). This is similar to counter values over which the STOP bits are encoded corresponding to the binary strings. Jiang Figure 16 further discloses a flowchart for the bit allocation for encoding/decoding where the information bits are encoded and transmitted (Jiang Figure 16, steps 1610, 1620; paragraphs 0185, 0187 and 0188). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Gaspar to have the features of encoding STOP bits over respective resource elements of a counter space, wherein the counter space is a portion of a resource grid having a predetermined size in the time domain and in the frequency domain, wherein counter values are associated with respective resource elements of the counter space according to a predetermined rule, and wherein the counter values of the re-source elements over which the STOP bits are encoded correspond to the M binary string values; and transmitting the encoded STOP bit; as taught by Jiang. The suggestion/motivation would have been to provide improved coding performance and reduce storage and/or computations (Jiang paragraph 0119). Claims 8 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Gaspar in view of Jiang, and further in view of Zhang et al. (CN 101925119A, hereinafter Zhang. English translation is provided). Regarding claim 8, Gaspar and Jiang disclose the apparatus of claim 1. Gaspar and Jiang do not expressly disclose wherein the at least one memory and computer program code are configured to, with the at least one processor, cause the apparatus further at least to: transmit a START bit with the encoded STOP bits, the START bit defining the start of the counter space in the resource grid. However, in the same or similar field of invention Zhang discloses that for a block of data, the start bit and stop bit are set in the transmission of the resource elements (Zhang paragraphs 0022-0023). For a plurality of divided blocks to be transmitted, start and stop bits are included (Zhang paragraph 0067). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Gaspar and Jiang to have the feature of transmitting a START bit with the encoded STOP bits, the START bit defining the start of the counter space in the resource grid; as taught by Zhang. The suggestion/motivation would have been to improve system capacity (Zhang paragraph 0001). Regarding claim 19, Gaspar and Jiang disclose the apparatus of claim 12. Gaspar and Jiang do not expressly disclose wherein the at least one memory and computer program code are configured to, with the at least one processor, cause the apparatus further at least to: receive a START bit with the STOP bits, the START bit defining the start of the counter space in the resource grid. However, in the same or similar field of invention Zhang discloses that for a block of data, the start bit and stop bit are set in the transmission of the resource elements (Zhang paragraphs 0022-0023). For a plurality of divided blocks to be transmitted, start and stop bits are included (Zhang paragraph 0067). Zhang further discloses that a receiving module receives the resource elements in the divided blocks along with start and stop bits (Zhang paragraph 0025). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Gaspar and Jiang to have the feature of receiving a START bit with the STOP bits, the START bit defining the start of the counter space in the resource grid; as taught by Zhang. The suggestion/motivation would have been to improve system capacity (Zhang paragraph 0001). Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Gaspar in view of Jiang, and further in view of Gong et al. (CN 111385748A, hereinafter Gong. English translation is provided). Regarding claim 20, Gaspar and Jiang disclose the apparatus of claim 12. Gaspar and Jiang do not expressly disclose wherein the at least one memory and computer program code are configured to, with the at least one processor, cause the apparatus further at least to: broadcast information defining the start of the counter space. However, in the same or similar field of invention, Gong discloses that the first transmission resource information includes two parts of resource information, where the second resource information is used to indicate resources that can be used by the receiving node when broadcasting layered modulation data in the communication system shown in fig. 1, and includes at least one of symbol information in time domain resource information, physical resource block information in frequency domain resource information, space domain resource information, and coded modulation information; for example, the physical resource block information includes starting physical resource block information and ending physical resource block information for mapping the layered modulation data (Gong page 15, first paragraph). This indicates broadcasting information defining the start of the counter space. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Gaspar and Jiang to have the feature of broadcasting information defining the start of the counter space; as taught by Gong. The suggestion/motivation would have been to improve the broadcast transmission efficiency of multi-layer data (Gong page 2; summary section, first paragraph). Allowable Subject Matter Claims 3-7, 9-10 and 14-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 3 would be allowable because the closest prior art, either alone or in combination, fails to anticipate or render obvious the features of when M is greater than or equal to 2, encode additional information over a further portion of the resource grid to indicate position order of the STOP bits in the counter space for the respective M binary strings; and transmit the additional information; in combination with all other limitations in the base claim and any intervening claims. Claim 5 would be allowable because the closest prior art, either alone or in combination, fails to anticipate or render obvious the features of when the counter values are in one-to-one association with respective resource elements of the counter space, encode the STOP bits over respective resource elements of the counter space by means of non-coherent modulation of sub-carriers of respective resource elements; in combination with all other limitations in the base claim and any intervening claims. Claim 6 would be allowable because the closest prior art, either alone or in combination, fails to anticipate or render obvious the features of when the counter values are in many-to-one association with respective resource elements of the counter space, encode the STOP bits over respective resource elements of the counter space by means of coherent modulation of sub-carriers of respective resource elements; in combination with all other limitations in the base claim and any intervening claims. Claim 7 would be allowable because the closest prior art, either alone or in combination, fails to anticipate or render obvious the features of wherein the predetermined rule comprises assigning increasing counter values to increasing sub-carrier indexes first and next increasing time indexes of the resource grid; in combination with all other limitations in the base claim and any intervening claims. Claim 9 would be allowable because the closest prior art, either alone or in combination, fails to anticipate or render obvious the features of use, when encoding the STOP bits over respective resource elements of the counter space, fractional time shifts; in combination with all other limitations in the base claim and any intervening claims. Claim 10 would be allowable because the closest prior art, either alone or in combination, fails to anticipate or render obvious the features of use, when encoding the STOP bits over respective resource elements of the counter space, fractional frequency shifts; in combination with all other limitations in the base claim and any intervening claims. Claim 14 would be allowable because the closest prior art, either alone or in combination, fails to anticipate or render obvious the features of when M is greater than or equal to 2, receive additional information over a further portion of the resource grid, the additional information indicating position order of the STOP bits in the counter space for the respective M binary strings; and decode the M binary string values according to the additional information; in combination with all other limitations in the base claim and any intervening claims. Claim 16 would be allowable because the closest prior art, either alone or in combination, fails to anticipate or render obvious the features of when the counter values are in one-to-one association with respective resource elements of the counter space, decode the received STOP bits by means of non-coherent demodulation of sub-carriers of respective resource elements; in combination with all other limitations in the base claim and any intervening claims. Claim 17 would be allowable because the closest prior art, either alone or in combination, fails to anticipate or render obvious the features of when the counter values are in many-to-one association with respective resource elements of the counter space, decode the received STOP bits by means of coherent demodulation of sub-carriers of respective resource elements; in combination with all other limitations in the base claim and any intervening claims. Claim 18 would be allowable because the closest prior art, either alone or in combination, fails to anticipate or render obvious the features of wherein the pre-determined rule comprises assigning increasing counter values to increasing sub-carrier indexes first and next increasing time indexes of the resource grid; in combination with all other limitations in the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAUMIT SHAH whose telephone number is (571)272-6959. The examiner can normally be reached Monday - Friday 9 am - 6 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, EDAN ORGAD can be reached at (571) 272-7884. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SAUMIT SHAH/Primary Examiner, Art Unit 2414
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Prosecution Timeline

Jul 30, 2024
Application Filed
Jul 07, 2026
Non-Final Rejection mailed — §103, §112 (current)

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Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
98%
With Interview (+10.6%)
2y 4m (~4m remaining)
Median Time to Grant
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