DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 13 are rejected under 35 U.S.C. 103 as being unpatentable over Erine et al (Multi Channel AlGaN/GaN In Plane Gate FET, IEEE Electron Device Letters Vol 41., No 3, March 2020-submitted IDS).
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Regarding claim 1, Erine discloses a two-dimensional electron gas field-effect transistor, referred to as TEGFET, comprising: a drain Fig 1; a source and at least one channel Fig 1;comprised in a heterostructure formed by a stack of at least two layers of semiconductor Page 2, Column 1; the at least one channel connects, along its largest dimension Fig 1, referred to as the length (L) of the at least one channel, the source and the drain Fig 1; said TEGFET: comprises at least two side gates Fig 1 arranged on either side of the at least one channel and each arranged opposite one side Fig 1 of the at least one channel, said sides of the at least one channel comprise a smaller dimension of said at least one channel Fig 1, referred to as the thickness Fig 1 of the at least one channel, extending along an axis in which the at least two semiconductor layers are stacked and extending perpendicularly to the length of the at least one channel; and does not comprise a gate positioned below or above the at least one channel with respect to an axis perpendicular to a plane, known as the channel plane, along which the at least one channel extends between the source and the drain, said channel plane being perpendicular to the thickness of the at least one channel Fig 1, said TEGFET being characterized including: a width of the at least one channel, and/or - a length of a segment of the at least one channel, located opposite the at least two side gates, wherein the conductivity is modulated and/or controlled, and/or - a length of the at least two side gates, the length of the at least two side gates being the dimension of the at least two side gates in a direction parallel to the length of the at least one channel Fig 1. Although Erine discloses all the limitations but silent on the dimensions of the channel/gate. It would have been obvious to one having ordinary skill in the art at the time the invention was made to the dimensions of the device components, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (1955). It has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F. 2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F .2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F .2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F .2d 669, 149 USPQ 47 (CCPA 1966).
Regarding claim 2, Erine discloses wherein none of the side gates of the at least two side gates is in contact or has a part or interface in common with the at least one channel Fig 1.
Regarding claim 3, Erine discloses wherein said at least two side gates (5) are arranged, to modulate and/or modify and/or vary the potential in the at least one channel along an axis , known as the lateral axis, comprised in the channel plane and perpendicular to the axis connecting source and drain Page 1 Fig 1.
Regarding claim 4, Erine discloses comprising a dielectric arranged between each of the side gates , of the at least two side gates, and the at least one channel Fig 1.
Regarding claim 5, Erine discloses, wherein the dielectric is arranged in the form of a recess Fig 1.
Regarding claim 6, Erine discloses wherein the recess comprises a gas Fig 1.
Regarding claim 7, Erine discloses wherein the at least two side gates are composed of a semiconductor material Page 2, Column 1 Fig 1.
Regarding claim 8, Erine discloses wherein the semiconductor material making up the at least two side gates comprises metal atoms diffused into the semiconductor material Page 2, Column 1 Fig 1.
Regarding claim 9, Erine discloses wherein one of the side gates (5) is electrically connected to the source Page 2, Column 1 Fig 1.
Regarding claim 10, Erine discloses method for modulating the conductivity of at least one channel of a two-dimensional electron gas field-effect transistor Fig 1, so-called TEGFET, said method comprising the steps of: - applying a potential difference between a source and a drain of the TEGFET Page 1, column 2 and Page 2 Column 2; applying: the same potential difference between at least one of the side gates of the TEGFET Page 1, column 2 and Page 2 Column 2, from among at least two side gates arranged laterally on either side of the at least one channel of the TEGFET Page 1, column 2 and Page 2 Column 2, and the source of the TEGFET Page 1, column 2 and Page 2 Column 2; and/or the same potential on one or each of the side gates and on the source of the TEGFET- and/or a potential difference between at least one of the side gates of the TEGFET and the source of the TEGFET modulating and/or modifying and/or varying the electron density of the two- dimensional electron gas and/or modulating the current non-uniformly over a width of the at least one channel Fig 1 Page 1, column 2 and Page 2 Column 2; the at least one channel connects, along the largest dimension of the at least one channel, called the length (L) of the at least one channel, the source and the drain of the TEGFET and the TEGFET does not comprise a gate positioned below or above the at least one channel with respect to an axis perpendicular to a plane, called channel plane Fig 1, in which the at least one channel extends between the source and the drain Fig 1, said channel plane being perpendicular to the smallest dimension of the at least one channel, called the thickness of the at least one channel, extending along an axis along which are stacked at least two semi-conductor layers Fig 1 forming a heterostructure wherein the at least one channel is comprised and extending perpendicularly to the length of the at least one channel; each of the at least two side gates is arranged opposite a side Fig 1 of the at least one channel, said sides of the at least one channel comprise the thickness (e) of the at least one channel; the width of the channel and/or a length of a segment of the at least one channel, located opposite the at least two side gates, wherein the conductivity is modulated and/or controlled Fig 1 Although Erine discloses all the limitations but silent on the dimensions of the channel/gate. It would have been obvious to one having ordinary skill in the art at the time the invention was made to the dimensions of the device components, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (1955). It has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F. 2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F .2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F .2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F .2d 669, 149 USPQ 47 (CCPA 1966).
Regarding claim 11, Erine discloses comprising the step of modulating and/or modifying and/or varying the potential and/or conductivity in at least one channel along a so-called lateral axis (lying in the channel plane and perpendicular to the axis connecting source and drain, by applying the same potential difference between at least one of the side gates and the source and/or by applying the same potential to one or each of the side gates and the source and/or by applying a potential difference between at least one of the side gates, or between each of the side gates, and the source Fig 1 Page 1, column 2 and Page 2 Column 2-Page 3.
Regarding claim 12, Erine discloses comprising the step of modulating and/or modifying and/or varying the potential in the at least one channel and/or the conductivity of the two-dimensional electron gas non-uniformly along a width of the at least one channel, the width of the at least one channel ex-tends along an axis perpendicular to the length of the at least one channel and perpendicular to the thickness of the at least one channel, by applying the same potential difference between at least one side gate and the source and/or by applying the same potential to one or each of the side gates and the source and/or by applying a potential difference between at least one of the side gates, or between each of the side gates, and the source Fig 1 Page 1, column 2 and Page 2 Column 2-Page 3.
Regarding claim 1, Erine discloses method for manufacturing a two-dimensional electron gas field-effect transistor (1), referred to as a TEGFET, said manufacturing method comprises a single annealing step for forming Page 2, column 1, simultaneously in a single step, distinct ohmic contacts between: a first metal layer Page 2, column 1, intended to form an electrical contact, and a drain of the TEGFET Page 2, column 1; and a second metal layer Page 2, column 1, intended to form an electrical contact, and a source (4) of the TEGFET Page 2, column 1 Fig 1; and a third metal layer (9, 91) Page 2, column 1 Fig 1, intended to form an electrical contact, and at least two side gates of the TEFGET Page 2, column 1 Fig 1, arranged laterally on either side of at least one channel of the TEGFET and each arranged facing a side 1 Fig 1 of the at least one channel, said sides of the at least one channel comprise a smaller dimension of said at least one channel, referred to as the thickness of the at least one channel, extending along an axis along which the at least two semiconductor layers are stacked and extending perpendicular to a length of the at least one channel Fig 1; an annealing time and temperature are chosen so that metal atoms diffuse from each of the metal layers into the semiconductor layers Fig 1. Although Erine discloses all the limitations but silent on the dimensions of the channel/gate. It would have been obvious to one having ordinary skill in the art at the time the invention was made to the dimensions of the device components, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (1955). It has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F. 2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F .2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F .2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F .2d 669, 149 USPQ 47 (CCPA 1966).
Conclusion
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/CHRISTINE A ENAD/Primary Examiner, Art Unit 2811
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