DETAILED ACTION
This correspondence is in response to the communications received 07/30/2024. Claims 7, 10, 11, 15, 17, 18, and 54 have been amended. Claims 20-53 have been canceled. Claims 1-19 and 54 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 01/23/2024 and 10/22/2025 have been considered by the examiner and made of record in the application file.
Specification
Applicant is reminded of the proper language and format for an abstract of the disclosure.
The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words in length. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details.
The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, “The disclosure concerns,” “The disclosure defined by this invention,” “The disclosure describes,” etc. In addition, the form and legal phraseology often used in patent claims, such as “means” and “said,” should be avoided.
The abstract of the disclosure is objected to because it includes the legally prohibited phraseology “the present disclosure provides” in line 1. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
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Regarding claim 1, a display panel (100), comprising:
a base substrate (101);
an active layer (102), a gate electrode (103) and a source-drain electrode layer (104) which are sequentially stacked on the base substrate (see Fig. 1A); and
a planarization layer (105), arranged at a side of the source-drain electrode layer away from the base substrate (see Fig. 1A),
wherein an orthographic projection of the gate electrode on the base substrate is located within orthographic projections of the source-drain electrode layer and the active layer on the base substrate (see Fig. 1A), and in a direction perpendicular to a main surface of the base substrate, a thickness of the source-drain electrode layer is greater than a thickness of the gate electrode ("setting the thickness of the source-drain electrode layer 104 to be greater than the thickness of the gate electrode 103 can further reduce the influence of the step difference caused by the gate electrode 103 with a certain thickness on the flatness of the planarization layer 105", [0086]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 54 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshida (US 20190296050 A1, published 09/26/2019) in view of Kishimoto et al (US 20220246703 A1, published 08/04/2022).
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Regarding claim 1, Figs. 1, 8A, and 8B of Yoshida disclose a display panel (“The active matrix substrate 1000 has a display region DR, and a region (the non-display region or bezel region) FR other than the display region DR. The display region DR includes pixel regions Pix arranged in a matrix pattern. The pixel region Pix is a region corresponding to a pixel of the display device”, [0061]), comprising:
a base substrate (“substrate 1”, [0143]);
an active layer (“crystalline silicon semiconductor layer 30 as the active layer”, [0140]), a gate electrode (“gate electrode GE”, [0140]) and a source-drain electrode layer (together “source electrode SE”, [0142], “source bus line SL”, [0143], and “drain electrode DE”, [0142] form a source-drain electrode layer) which are sequentially stacked on the base substrate (as seen in Fig. 8B, 30, GE, and SE/DE are sequentially stacked on 1); and
a planarization layer (“upper insulating layer 13”, [0143], Yoshida does not disclose that 13 is a planarization layer, however a secondary reference will be used below to connect 13 and the planarization layer), arranged at a side of the source-drain electrode layer away from the base substrate (as seen in Fig. 8B, 13 is arranged at a side of SE/DE away from 1),
wherein an orthographic projection of the gate electrode on the base substrate is located within orthographic projections of the source-drain electrode layer and the active layer on the base substrate (as seen in Figs. 8A and 8B, an orthographic projection of GE on 1 is located within orthographic projections of SE/DE and 30 on 1).
Figs. 1, 8A, and 8B of Yoshida fail to disclose “a planarization layer,
in a direction perpendicular to a main surface of the base substrate, a thickness of the source-drain electrode layer is greater than a thickness of the gate electrode.”
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However, in a similar field of endeavor, Figs. 1 and 2C of Kishimoto teaches a planarization layer (“an insulating layer is provided between the drive circuit and the organic light-emitting element as described previously, and the insulating layer makes it possible to achieve planarization of the base for the organic light-emitting element as well as blocking of moisture and electrical isolation of the drive circuit and the organic light-emitting element”, [0030], thus 13 of Yoshida can be used as a planarization layer).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a planarization layer” as taught by Kishimoto in the system of Yoshida for the purpose of protecting the circuit elements from moisture or electrical interference.
Figs. 1, 8A, and 8B of Yoshida in combination with Kishimoto fail to disclose “in a direction perpendicular to a main surface of the base substrate, a thickness of the source-drain electrode layer is greater than a thickness of the gate electrode.”
However, in a similar field of endeavor, Figs. 7A-7E of Yoshida teach in a direction perpendicular to a main surface of the base substrate, a thickness of the source-drain electrode layer (“The thickness of the source electrode SE and the drain electrode DE is 100 nm or more and 500 nm or less”, [0120]) is greater than a thickness of the gate electrode (“a conductive film (thickness: 60 nm or more and 700 nm or less) 7′ to be the gate electrode are deposited”, [0113], thus SE/DE can be up to 500 nm in thickness and GE can be as thin as 60 nm, whereby a thickness of SE/DE is greater than a thickness of GE).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “in a direction perpendicular to a main surface of the base substrate, a thickness of the source-drain electrode layer is greater than a thickness of the gate electrode” as taught by Figs. 7A-7E of Yoshida in the system of Figs. 1, 8A, and 8B of Yoshida in combination with Kishimoto for the purpose of specifying compatible electrode thicknesses.
Regarding claim 2, Figs. 1, 7A-7E, 8A, and 8B of Yoshida in combination with Figs. 1 and 2C of Kishimoto disclose the display panel according to claim 1, Figs. 1, 8A, and 8B of Yoshida further disclose wherein,
a gate insulating layer (“gate insulating layer 5”, [0140]) is arranged between the active layer and the gate electrode (as seen in Fig. 8B, 5 is arranged between 30 and GE), and an interlayer insulating layer (“lower insulating layer 11”, [0142]) arranged between the gate electrode and the source-drain electrode layer (as seen in Fig. 8B, 11 is between GE and SE/DE and is therefore an interlayer insulating layer);
the source-drain electrode layer comprises a first source-drain electrode (together SE and SL are a first source-drain electrode) and a second source-drain electrode (DE is a second source-drain electrode) which are oppositely arranged (as seen in Fig. 8B, SE is oppositely arranged to DE relative to 30);
the first source-drain electrode is electrically connected with the active layer through a first via hole structure that sequentially penetrates the interlayer insulating layer and the gate insulating layer (as seen in Fig. 8B, SE is electrically connected with 30 through “source opening 11s”, [0142], that sequentially penetrates 11 and 5), and an orthographic projection of the gate electrode on the base substrate is located within an orthographic projection of the first source-drain electrode on the base substrate (as seen in Figs. 8A and 8B, an orthographic projection of GE on 1 is located within orthographic projections of SE/SL on 1);
the second source-drain electrode is electrically connected with the active layer through a second via hole structure that sequentially penetrates the interlayer insulating layer and the gate insulating layer (as seen in Fig. 8B, DE is electrically connected with 30 through “source opening 11s”, [0143], that sequentially penetrates 11 and 5).
Regarding claim 3, Figs. 1, 7A-7E, 8A, and 8B of Yoshida in combination with Figs. 1 and 2C of Kishimoto disclose the display panel according to claim 2, Figs. 1, 8A, and 8B of Yoshida further disclose wherein an end portion of the first source-drain electrode away from the second source-drain electrode is electrically connected with the active layer through the first via hole structure (as seen in Fig. 8B, the bottom end of SE which is away from DE is electrically connect to 30 through 11s).
Regarding claim 54, Figs. 1, 7A-7E, 8A, and 8B of Yoshida further disclose a display device (“The active matrix substrate 1000 has a display region DR, and a region (the non-display region or bezel region) FR other than the display region DR. The display region DR includes pixel regions Pix arranged in a matrix pattern. The pixel region Pix is a region corresponding to a pixel of the display device”, [0061]) comprising the display panel according to claim 1 disclosed by Figs. 1, 7A-7E, 8A, and 8B of Yoshida in combination with Figs. 1 and 2C of Kishimoto.
Claims 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshida (US 20190296050 A1, published 09/26/2019) in view of Kishimoto et al (US 20220246703 A1, published 08/04/2022) in view of Kim (US 20220208935 A1, published 06/30/2022) in view of Yan (US 11,532,246 B2, published 12/20/2022).
Regarding claim 4, Figs. 1, 7A-7E, 8A, and 8B of Yoshida in combination with Figs. 1 and 2C of Kishimoto disclose the display panel according to claim 2.
Yoshida in combination with Kishimoto fails to disclose “further comprising a plurality of data lines, wherein the plurality of data lines are arranged in the same layer as the source-drain electrode layer, and the plurality of data lines are electrically connected with corresponding second source-drain electrodes.”
However, in a similar field of endeavor, Figs. 4-11 of Kim teach further comprising a plurality of data lines (“first data line DL1”, [0111], “second data line DL2”, [0112], and “third data line DL3”, [0113])… and the plurality of data lines are electrically connected with corresponding second source-drain electrodes (“first data line DL1 may be connected to a second connection electrode BE2 of the source-drain layer SDL through a twenty-second contact hole CNT22, and the second connection electrode BE2 may be connected to the drain electrode DE2 of the second transistor ST2 of the first pixel SP1”, [0111], “The second data line DL2 may be connected to a fifth connection electrode BE5 of the source-drain layer SDL through a twenty-fourth contact hole CNT24, and the fifth connection electrode BE5 may be connected to the drain electrode DE2 of the second transistor ST2 of the second pixel SP2”, [0112], and “The third data line DL3 may be connected to an eighth connection electrode BE8 of the source-drain layer SDL through a twenty-sixth contact hole CNT26, and the eighth connection electrode BE8 may be connected to the drain electrode DE2 of the second transistor ST2 of the third pixel SP3The third data line DL3 may be connected to an eighth connection electrode BE8 of the source-drain layer SDL through a twenty-sixth contact hole CNT26, and the eighth connection electrode BE8 may be connected to the drain electrode DE2 of the second transistor ST2 of the third pixel SP3”, [0113], thus each data line DL1-DL3 is connected to a corresponding drain electrode DE2 where DE2 of Kim is equivalent to DE of Yoshida).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “further comprising a plurality of data lines, wherein the plurality of data lines are arranged in the same layer as the source-drain electrode layer, and the plurality of data lines are electrically connected with corresponding second source-drain electrodes” as taught by Kim in the system of Yoshida in combination with Kishimoto for the purpose of providing data lines to control pixel output.
Yoshida in combination with Kishimoto and Kim fails to disclose “wherein the plurality of data lines are arranged in the same layer as the source-drain electrode layer”.
However, in a similar field of endeavor, Fig. 1 of Yan teaches wherein the plurality of data lines are arranged in the same layer as the source-drain electrode layer (“The source-drain layer 128 is patterned by an etching process to form a source and a drain of each thin-film transistor, data lines, and shared electrode lines”, col. 5, lines 64-67, thus DL1-DL3 of Kim can be formed on the same layer as SE/DE of Yoshida).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “wherein the plurality of data lines are arranged in the same layer as the source-drain electrode layer” as taught by Yan in the system of Yoshida in combination with Kishimoto and Kim for the purpose of simplifying the manufacturing process by forming multiple wiring elements in the etch process.
Regarding claim 5, Figs. 1, 7A-7E, 8A, and 8B of Yoshida in combination with Figs. 1 and 2C of Kishimoto, Figs. 4-11 of Kim, and Fig. 1 of Yang disclose the display panel according to claim 4, Fig. 2C of Kishimoto further discloses further comprising a pixel defining layer (“insulating bank 42”, [0039], as seen in Fig. 2C, 42 defines the pixel formed by “organic light-emitting element 40”, [0039]) arranged at a side of the planarization layer away from the base substrate (as seen in Fig. 2C, 42 is arranged at a side of “planarizing layer 30”, [0039], away from “substrate 10”, [0039], where 30 and 10 of Kishimoto are equivalent to 13 and 1 of Yoshida respectively), wherein the pixel defining layer comprises a main body part and an opening area between adjacent main body parts (as seen in Fig. 2C, 42 has a main body part, and an opening area between adjacent main body parts where “organic light-emitting layer 43”, [0039], is located).
Regarding claim 6, Figs. 1, 7A-7E, 8A, and 8B of Yoshida in combination with Figs. 1 and 2C of Kishimoto, Figs. 4-11 of Kim, and Fig. 1 of Yang disclose the display panel according to claim 5, Fig. 2C of Kishimoto further discloses further comprising a first electrode (“a first electrode (for example, an anode) 41”, [0039]) arranged at a side of the planarization layer away from the base substrate (as seen in Fig. 2C, 41 is arranged at a side of 30 away from 10), wherein the first electrode is arranged in the opening area (as seen in Fig. 2C, 41 is arranged in the opening area between outer edges of 42), and the first electrode is electrically connected with the first source-drain electrode through a third via hole structure penetrating through the planarization layer (as seen in Fig. 2C, 41 is electrically connected to “source electrode 25”, [0038], through “contact hole 30a”, [0056], penetrating through 30, where 25 of Kishimoto is equivalent to SE of Yoshida).
Allowable Subject Matter
Claims 7-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The prior art of record does not teach or fairly suggest the display panel as recited in the claims of the instant application.
Regarding claim 7, the prior art of Yoshida (US 20190296050 A1) in view of Kishimoto et al (US 20220246703 A1) in view of Kim (US 20220208935 A1) in view of Yan (US 11,532,246 B2) discloses a similar display panel but fails to disclose the specific claims of the instant application regarding the relationship of the sizes of the first through third metal areas e.g. “an orthographic projection of the first source-drain electrode corresponding to the first color sub-pixel on the base substrate has a first metal area SM1, an orthographic projection of the first source-drain electrode corresponding to the second color sub-pixel on the base substrate has a second metal area SM2, and an orthographic projection of the first source-drain electrode corresponding to the third color sub-pixel on the base substrate has a third metal area SM3, the first metal area SM1 is less than or equal to the second metal area SM2, and the second metal area SM2 is less than the third metal area SM3”.
Claims 8-19 are allowable by virtue of their dependence on claim 7.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN M KUPP whose telephone number is (571)272-5608. The examiner can normally be reached Monday - Friday, 7:00 am - 4:00 pm PT.
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/BENJAMIN MICHAEL KUPP/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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