Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Prior Art of Record
The applicant's attention is directed to additional pertinent prior art cited in the accompanying PTO-892 Notice of References Cited, which, however, may not be currently applied as a basis for the following rejections. While these references were considered during the examination of this application and are deemed relevant to the claimed subject matter, they are not presently being applied as a basis for rejection in this Office action. The pertinence of these documents, however, may be revisited, and they may be applied in subsequent Office actions, particularly in light of any amendments or further clarification of the claimed invention.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-8, 11-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Matsumoto et al. (US 20230143387 A1).
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CLAIM 1. Matsumoto teaches a solid state imaging device comprising: a pixel separation unit 310/304 that partitions a first surface of a semiconductor substrate into a plurality of first regions arrayed in a matrix shape (Fig. 1 & 2);
an in-pixel separation unit 304 that divides each of the first regions into at least two second regions (Fig. 2);
an etching stopper region 306 (The functional description lacks necessary structural limitations. Because the etch stop is defined solely by a material difference (i.e., varying etch rates), the specification implies the etch stop may simply be an undifferentiated portion of the substrate. Furthermore, the term “region” lacks definitive boundaries, rendering it subjective and failing to distinguish the claimed invention from the prior art.) disposed in at least a partial space between the pixel separation unit and the in-pixel separation unit in a plane parallel to the first surface and in a direction perpendicular to a direction in which the at least two second regions divided by the in-pixel separation unit are arrayed (Fig. 1, 2, 6-15 & 79);
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a photoelectric conversion unit 300a/300b disposed in each of the second regions; and a transfer transistor TR [400a/400b are transfer gates] (Fig. 87 & ¶342) connected to each of the photoelectric conversion units.
CLAIM 2. Matsumoto teaches a solid state imaging device according to claim 1, wherein the etching stopper region is made of a material in which etch selectivity to a constituent material of the in-pixel separation unit is secured (This limitation does not provide any structural distinction because it merely states a functional requirement rather than a concrete physical structure.).
CLAIM 3. Matsumoto teaches the solid state imaging device according to claim 1, wherein the etching stopper region is a partial region of the semiconductor substrate (Fig. 3).
CLAIM 4. Matsumoto teaches the solid state imaging device according to claim 1, wherein the in-pixel separation unit 308 extends from the first surface of the semiconductor substrate toward a second surface on an opposite side to the first surface, and does not reach the second surface (Fig. 21).
CLAIM 5. Matsumoto teaches the solid state imaging device according to claim 1, wherein the in-pixel separation unit contains at least one of diamond, diamond-like carbon (DLC), titanium oxide (TiO.sub.2), cerium oxide (CeO.sub.2), iron oxide (Fe.sub.2O.sub.3), silicon nitride (SiN), gallium arsenide (GaAs), gallium phosphide (GaP), aluminum arsenide (AlAs), aluminum antimonide (AlSb), indium phosphide (InP), hexagonal silicon carbide (4H-SiC), hexagonal silicon carbide (6H-SiC), cubic silicon carbide (3C-SiC), zinc selenide (ZnSe), aluminum antimonide arsenide (AlSbAs), aluminum antimonide phosphide (AlSbP), indium aluminum phosphide (AlInP), gallium arsenide phosphide (GaAsP), indium gallium phosphide (InGaP), and aluminum gallium arsenide (GaAlAs) (¶162, 194…).
CLAIM 6. Matsumoto teaches the solid state imaging device according to claim 1, wherein the pixel separation unit contains at least one of silicon oxide (SiO.sub.2), tungsten (W), and aluminum (Al) (¶162, 194…).
CLAIM 7. Matsumoto teaches the solid state imaging device according to claim 1, wherein the in-pixel separation unit has a shape in which a width of a top surface located on a second surface side on an opposite side to the first surface of the semiconductor substrate is narrower than a width of a bottom surface located on the first surface side (Fig. 59, 61, 62, 63 64, 65, 66, 69, and/or 82 – The listed figures all show different embodiments where the width of the in-pixel separation may have a wider or narrower with at the upper and/or lower surface. Selection of the shape as broadly recited, does not provide a distinction over the listed optional variations.) .
CLAIM 8. Matsumoto teaches the solid state imaging device according to claim 1, wherein the pixel separation unit optically and electrically separates the first regions from each other, and the in-pixel separation unit electrically separates the at least two second regions from each other (Figs, 1, 2 and 14 – Note: Regions does not provide explicit boundaries. Fig. 4 depicts quadrants meeting one interpretation, while figure 2 may subjectively viewed as quadrants also meeting the broad scope of the claim under BRI. As such, the limitation does not provide any further clear and explicit structural distinction over the prior art.).
CLAIM 11. Matsumoto teaches a solid state imaging device comprising:
a pixel separation unit that partitions a first surface of a semiconductor substrate into a plurality of first regions arrayed in a matrix shape (Matsumoto Figs. 1& 2);
an in-pixel separation unit that divides each of the first regions into at least two second regions (Matsumoto Figs. 1& 2); the in-pixel separation unit including an overflow path region 320 - ¶161 for allowing charge accumulated in one of the at least two second regions to flow into at least another second region (Matsumoto Figs. 3-4);
a photoelectric conversion unit disposed in each of the second regions (Matsumoto Figs. 1& 2); and a transfer transistor 400a/400b [transfer gates of the transfer transistors) connected to each of the photoelectric conversion units, wherein at least a part of the in-pixel separation unit has an impurity concentration profile adjusted such that a potential barrier becomes higher toward a center of the in-pixel separation unit and that the potential barrier becomes higher as a distance from the overflow path increases in a plane parallel to the first surface (Matsumoto Figs. 27-35 & 37& ¶33);.
CLAIM 12. Matsumoto teaches the solid state imaging device according to claim 11, wherein the overflow path region has an impurity concentration profile adjusted to be substantially uniform both in the plane parallel to the first surface and in a plane perpendicular to the first surface (Matsumoto Fig. 30)
CLAIM 13. Matsumoto teaches the solid state imaging device according to claim 11, wherein at least a part of the in-pixel separation unit is an epitaxial film formed using graded epitaxial technique capable of controlling an impurity concentration in a stepwise manner (Method of manufacture does not provide a clear and explicit structural distinction. Note: ¶310 discloses layers may be formed by various epitaxy processes.).
CLAIM 14. Matsumoto teaches the solid state imaging device according to claim 11, wherein the impurity has a polarity opposite to a polarity of charge generated in the photoelectric conversion unit (Matsumoto ¶163 & 165).
CLAIM 15. Matsumoto teaches the solid state imaging device according to claim 11, wherein the impurity has high potential energy with respect to charge generated in the photoelectric conversion unit (The limitation does not provide further structural distinction, as it is a result of the previously recited structure.).
CLAIM 16. Matsumoto teaches the solid state imaging device according to claim 11, wherein at least a part of the in-pixel separation unit is a semiconductor layer containing an impurity having a polarity opposite to a polarity of an impurity contained in the semiconductor substrate (Matsumoto ¶163 & 165).
CLAIM 17. Matsumoto teaches the solid state imaging device according to claim 11, wherein at least a part of the in-pixel separation unit includes at least one of a group IV semiconductor including at least one of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), and a group III-V semiconductor including at least two of boron (B), aluminum (Al), gallium (Ga), indium (In), nitrogen (N), phosphorus (P), arsenic (As), and antimony (Sb) (Matsumoto ¶162, 194…).
CLAIM 18. Matsumoto teaches the solid state imaging device according to claim 11, wherein the potential barrier is formed by a band offset (The limitation does not provide further structural distinction, as it is a result of the previously recited structure.).
CLAIM 19. Matsumoto teaches the solid state imaging device according to claim 11, wherein at least another part of the in-pixel separation unit has a same layer structure as a layer structure of the pixel separation unit (Matsumoto Figs. 1& 2).
CLAIM 20. Matsumoto teaches an electronic apparatus comprising: the solid state imaging device according to claim 1; and a processor that executes predetermined processing on image data output from the solid state imaging device (Fig. 91 & ¶353).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Matsumoto et al. (US 20230143387 A1) in view of Kim et al. (US 20210120198 A1).
CLAIM 9. Matsumoto teaches the solid state imaging device according to claim 1, however is silent on wherein the pixel separation unit is disposed on a surface in contact with the semiconductor substrate and includes a fixed charge film having negative fixed charge.
Kim et al. teaches that negative fixed charge layers are known additions to pixel separation layers (Paragraph [0063]). Specifically, Kim describes a pixel separation structure (150) comprising a conductive layer (152) and an insulation liner (154), where the insulation liner may comprise a metal oxide (e.g., hafnium, aluminum, or tantalum oxide) that acts as a negative fixed charge layer.
It would have been obvious to a person of ordinary skill in the art at the time of the invention to modify the pixel separation layer of Matsumoto by incorporating the negative fixed charge layer taught by Kim. This is because applying a known technique (incorporating a metal oxide negative fixed charge layer) to a known device ready for improvement (Matsumoto's pixel separation structure) to yield predictable results (improving isolation and passivation through fixed charges) is considered obvious under 35 U.S.C. § 103.
CLAIM 10. Matsumoto in view of Kim teaches the solid state imaging device according to claim 9, wherein the fixed charge film contains at least one of oxides of hafnium, zirconium, aluminum, tantalum, titanium, magnesium, yttrium, and lanthanoids (Kim ¶63).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JARRETT J STARK whose telephone number is (571)272-6005. The examiner can normally be reached 8-4 M-F.
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JARRETT J. STARK
Primary Examiner
Art Unit 2822
7/20/2026
/JARRETT J STARK/Primary Examiner, Art Unit 2898
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