DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/3/24 is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 4 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Arima (US 2011/0241724).
With respect to claim 1,
Figure 8 of Arima discloses a semiconductor device comprising:
a first flip-flop (FF11) configured to retain input data (FD1) in response to a clock signal (CLK) and to output first output data (IO11) based on the input data;
a second flip-flop (FF12) configured to retain the input data (FD1) in response to the clock signal (CLK) and to output second output data (IO12) based on the input data;
a third flip-flop (FF13) configured to retain the input data (FD1) in response to the clock signal (CLK) and to output third output data (IO13) based on the input data;
a majority circuit (MJR1) to which the first output data to the third output data are input (see Figure 8) and being configured to determine the most common logical value in the first output data to the third output data by majority decision making and to output data of the determined logical value as fourth output data (Paragraph 88); and
a switching circuit (CH1) to which the first output data (Mi1 – when Mi1 is the same value as IO11) and the fourth output data (Ma1) are input and being configured to output output data (QR1) based on the first output data or the fourth output data in response to a switching signal (TEST).
With respect to claim 4,
Arima further teaches a logic circuit configured to control supply of the clock signal to the second flip-flop and the third flip-flop (Paragraph 8).
Allowable Subject Matter
Claims 2-3 and 5-6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jany Richardson whose telephone number is (571)270-5074. The examiner can normally be reached Monday - Friday, 7:00am to 3:00pm.
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/JANY RICHARDSON/Primary Examiner, Art Unit 2844