Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to application No. 18/834,575 filed on September 11, 2026.
Priority
3. Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
4. Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS have been considered.
Specification
5. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: “Comprising Multiple Semiconductor Components with Holding Layer in Opening”.
Election/Restrictions
6. Applicant’s election without traverse of device claims 32-39, 57-62, Group I (PRD_GRP), in the reply filed on 09/11/2026 is acknowledged.
7. Claims 40-56 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to nonelected method claims 40-56, Group PROC_GRP, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 09/11/2026.
Claim Objections
8. Claims 32, 35-37, 57-62 are objected to because of the following informalities: the claims should be recited as follows to avoid indefiniteness, and/or perform proper alignment of the claim languages:
32. (Currently Amended) A semiconductor arrangement comprising:
at least one semiconductor component comprising a functional layer stack, the functional layer stack comprising:
a first layer of a first conductivity type;
a second layer of a second conductivity type arranged on the first layer;
an active zone located between the first layer and the second layer; and
an electrically conductive nanowire layer, wherein the electrically conductive nanowire layer is arranged at least in regions on a side of the second layer facing away from the first layer; and
a holding layer with at least one elevation,
wherein the at least one semiconductor component is arranged on the at least one elevation such that a cavity is formed between the at least one semiconductor component and the holding layer, and
wherein the electrically conductive nanowire layer is at least partially exposed.
35. (Currently Amended) The semiconductor arrangement according to claim 32, wherein the at least one semiconductor component further comprises a start layer arranged between the second layer and the electrically conductive nanowire layer.
36. (Currently Amended) The semiconductor arrangement according to claim 32, wherein the electrically conductive nanowire layer substantially covers an entire side of the second layer facing away from the first layer.
37. (Currently Amended) The semiconductor arrangement according to claim 32, wherein a plurality of nanowires is present separately from one another within the electrically conductive nanowire layer.
57. (Currently Amended) An optoelectronic device comprising:
a printed circuit board comprising a contact structure with a plurality of contact surfaces on a top surface; and
a plurality of semiconductor components, each arranged on one of the plurality of contact surfaces,
wherein each of the plurality of semiconductor components comprises an electrically conductive nanowire layer at least in certain regions on a bottom surface facing the contact structure, and
wherein the electrically conductive nanowire layer is in electrically conductive connection with one of the plurality of contact surfaces on the top surface of the printed circuit board.
58. (Currently Amended) The optoelectronic device according to claim 57, wherein the plurality of contact surfaces on the top surface of the printed circuit board comprise an electrically conductive nanowire layer.
59. (Currently Amended) The optoelectronic device according to claim 57, wherein each of the plurality of semiconductor components comprises an electrically conductive and at least semi-transparent contact layer on a side of the plurality of semiconductor components opposite the printed circuit board.
60. (Currently Amended) The optoelectronic device according to claim 57, wherein each of the plurality of semiconductor components comprises a start layer formed between a functional layer stack of the plurality of semiconductor components and the electrically conductive nanowire layer.
61. (Currently Amended) The optoelectronic device according to claim 57, wherein the electrically conductive nanowire layer of each of the plurality of semiconductor components substantially covers an entire bottom surface of a respective semiconductor component facing the contact structure.
62. (Currently Amended) The optoelectronic device according to claim 57, wherein a plurality of nanowires is present separately from one another within each of the plurality of nanowire layer.
Appropriate corrections are needed.
Claim Rejections - 35 USC § 102
9. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
10. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
11. Claims 57-59 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Wang et al. (US 2021/0175390 A1).
Regarding independent claim 57, Wang et al. teaches an optoelectronic device (para [0023]) comprising (Fig. 8):
a printed circuit board (200 called conductive carrier, para [0027]) comprising a contact structure (202, para [0044]) with a plurality of contact surfaces on a top surface (upper surface); and
a plurality of semiconductor components (102), each arranged on one of the plurality of contact surfaces,
wherein each of the semiconductor components (102) comprises an electrically conductive nanowire layer (104) at least in certain regions on a bottom surface facing the contact structure (202), and
wherein each electrically conductive nanowire layer (104) is in electrically conductive connection with one of the contact surfaces on the top surface (upper surface) of the printed circuit board (200).
Regarding claim 58, Wang et al. teaches wherein (Fig. 8), the plurality of contact surfaces on the top surface (upper surface) of the printed circuit board (200) comprise an electrically conductive nanowire layer (202: 202-1, 202-2).
Regarding claim 59, Wang et al. teaches wherein (Fig. 8), each of the semiconductor components (102) comprises an electrically conductive and at least semi-transparent contact layer (anisotropic conductive film-ACF, para [0028]) on a side of the semiconductor component (102) opposite the printed circuit board (200).
Claim Rejections - 35 USC § 103
12. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
13. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
14. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
15. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
a. Determining the scope and contents of the prior art.
b. Ascertaining the differences between the prior art and the claims at issue.
c. Resolving the level of ordinary skill in the pertinent art.
d. Considering objective evidence present in the application indicating obviousness or non-obviousness.
16. Claims 60-62 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 2021/0175390 A1) as applied to claim 57 above, and further in view of Hu et al. (US 2013/0285086 A1).
Regarding claim 60, Wang et al. teaches all of the limitations of claim 57 from which this claim depends.
Wang et al. teaches wherein (Fig. 8), each of the semiconductor components (102) comprises a start layer (208) formed between the semiconductor component (102) and the electrically conductive nanowire layer (104).
Wang et al. is silent to explicitly show wherein, a functional layer stack in the light emitting diode.
Hu et al. discloses wherein (Fig. 15), the functional layer stack (114/116/118) comprises multiple layers, such as n-type layer (114), active layer (116) and p-type layer (118) in the p-n diode layer (150).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Hu et al. while forming the LED element of Wang et al. in the GaN layer, in order to perform in a controlled fashion a predetermined electronic function (para [0055]).
Regarding claim 61, Wang et al. teaches all of the limitations of claim 57 from which this claim depends.
Wang et al. is silent to explicitly disclose wherein, the electrically conductive nanowire layer of each semiconductor component substantially covers an entire bottom surface of the respective semiconductor component facing the contact structure.
Hu et al. discloses wherein (Fig. 15), the electrically conductive nanowire layer (210) of each semiconductor component (150) substantially covers an entire bottom surface of the respective semiconductor component (150) facing the contact structure (410).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Hu et al. and modifying the semiconductor structure of Wang et al. by adding the bonding layer, in order to facilitate bonding, and to increase adhesion (para [0065]).
Regarding claim 62, Wang et al. teaches all of the limitations of claim 57 from which this claim depends.
Wang et al. is silent to explicitly disclose wherein, a plurality of nanowires is present separately from one another within each nanowire layer.
Hu et al. discloses wherein (Fig. 15), a plurality of nanowires (120 metallization stacks) is present separately from one another within each nanowire layer (210).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Hu et al. and modifying the semiconductor structure of Wang et al. by adding the metallization stack, in order to provide a topography which facilitates the formation of a continuous contact line (para [0065]).
Allowable Subject Matter
17. Claims 32-39 are allowed.
18. The following is an examiner’s statement of reasons for allowance:
Claim 32: the prior art of record alone or in combination neither teaches nor makes obvious a semiconductor arrangement comprising:
….
a holding layer with at least one elevation,
wherein the at least one semiconductor component is arranged on the at least one elevation such that a cavity is formed between the at least one semiconductor component and the holding layer, and
wherein the nanowire layer is at least partially exposed.
19. The prior arts made of record in PTO-892 and not relied upon are considered pertinent to applicant’s disclosure: the prior art, Wang et al. (US 2021/0175390 A1) is a close prior art, which describes electronic elements, depicts in Fig. 8 and comprises conductive carrier considered as the printed circuit board, conductive structure/contacts and multiple optical components as claimed, however, Wang et al. does not disclose the limitations in section 18, therefore, either by itself or in combination with other arts fail to disclose the above quoted limitations in section 18.
Examiner’s Note
20. Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular paragraphs and/or columns/lines in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
21. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DIDARUL MAZUMDER whose telephone number is (571)272-8823. The examiner can normally be reached M-F 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
22. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DIDARUL A MAZUMDER/Primary Examiner, Art Unit 2812
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