DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the plan view in the recited limitation of claim 8 of “a semiconductor layer overlapping the semiconductor in plan view and provided with the photoelectric conversion element” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 and 14 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation " the semiconductor layer" in lines 11-12 of the claim. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination the Examiner above interprets “the semiconductor layer” as “the semiconductor”.
Claim 14 recites the limitation "the semiconductor layer" in lines 6, 19 and 21. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination the Examiner above interprets “the semiconductor layer” as “the semiconductor”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1,3-4,6-9 and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Yamakawa (US 2021/0384237 A1, hereinafter Yamakawa ‘237) in view of Zang et al. (US 2022/0320162 A1, hereinafter Zang ‘162) in further view of Yorikado (US 2021/0352232 A1, hereinafter Yorikado ‘232) in view of the following arguments.
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With respect to Claim 1 Yamakawa ‘237 discloses a semiconductor device (Fig 1-7 and 18-22H) comprising:
first (25, Fig 19, Para [0171]) and second field-effect (24, Fig 19, Para [0171]) transistors,
wherein each of the first (25) and second field-effect transistors (24)(Para [0171] discloses 24 and 25 as field-effect transistors) includes
a channel formation portion (25C (channel for 25) and 24C (channel for 24), Fig 20B and Fig 20A respectively, Para [0172]) provided in a semiconductor (30S around 25C and 24C disclosed in Fig 20B and Fig 20A respectively, Para [0173]) including an upper surface (top of 25C and top of 24C shown in annotated Fig 20A/20B of Yamakawa ‘237) and side surfaces (sides of 25C and side of 24C shown in annotated Fig 20A/20B of Yamakawa ‘237),
a gate electrode (25G and 24G as shown in Fig 20B and 20A respectively, Para [0172]) provided over the upper surface (top of 25C and top of 24C shown in annotated Fig 20A/20B of Yamakawa ‘237) and the side surfaces (sides of 25C and side of 24C shown in annotated Fig 20A/20B of Yamakawa ‘237) in one direction (horizontal direction as shown in annotated Fig 20A/20B of Yamakawa ‘237) of the semiconductor (30S), and
a gate insulating film (251 (insulating film for 25) and 241 (insulating film for 24), Fig 20B and Fig 20A respectively, Para [0172]) provided between the semiconductor (30S) and the gate electrode (25G and 24G)( Fig 20B and 20A disclose gate insulating film provided between semiconductor and gate electrode),
But Yamakawa ‘237 fails to explicitly disclose a width, in the one direction, of the upper surface of the semiconductor layer overlapping the gate electrode of the first transistor is smaller than a width, in the one direction, of the upper surface of the semiconductor layer overlapping the gate electrode of the second transistor, and
Nevertheless, in a related endeavor (Fig 1-2, 4 and 9-11 of Zang ‘162), Zang ‘162 teaches a width (width of 494 as shown in annotated Fig 4 of Zang ‘162, Para [0036]), in the one direction (B2, Fig 4 of Zang ‘162, Para [0036]), of the upper surface of the semiconductor layer (Note Examiner’s above interpretation of “the semiconductor layer” as “the semiconductor”) overlapping the gate electrode of the first transistor (RS404, Fig 4 of Zang ‘162, Para [0036]) is smaller than a width (width of 492 as shown in annotated Fig 4 of Zang ‘162, Para [0036]), in the one direction (B2), of the upper surface of the semiconductor layer (Note Examiner’s above interpretation of “the semiconductor layer” as “the semiconductor”) overlapping the gate electrode of the second transistor (SF402, Fig 4 of Zang ‘162, Para [0036])(Zang ‘162 teaches in Para [0036] “a gate width of source follower gate 492 along axis B2 is larger than a gate width of row-select gate 494, one of ordinary skill in the art would recognize the gate width as the same as the channel width, the upper surface of the channel contacting the gate electrode), and
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Zang ‘162’s teaching of a width, in the one direction, of the upper surface of the semiconductor layer overlapping the gate electrode of the first transistor is smaller than a width, in the one direction, of the upper surface of the semiconductor layer overlapping the gate electrode of the second transistor into Yamakawa ‘237’s device. Yamakawa ‘237 discloses a semiconductor device with multiple finFET transistors with gate electrodes over the transistors and Yamakawa ‘237 and Yamakawa ‘237 discloses a width range for the channel region of one transistor (amplification transistor) but is silent on the channel width of the other transistors (select and reset). Zang ‘162 also teaches a semiconductor device with multiple FinFET transistors with gate electrodes over the transistors and Zang ‘162 further teaches a gate width of the source follower transistor (amplification) is larger than the gate width of the row select transistor (select transistor). The ordinary artisan would have been motivated to modify Yamakawa ‘237 in the manner set forth above, at least, because as Zang ‘162 teaches in Para [0036] that when the gate area of the source follower is greater than the gate area of the row select transistor, the random telegraph noise performance of the transistors can be improved. It would be obvious therefore for one of ordinary skill in the art to increase the gate width of the second transistor to be greater than the gate width of the first transistor as a mechanism to increase the gate area.
As incorporated, the teaching of the gate width of the first transistor (width of 494) being smaller than the gate width of the second transistor (width of 492) would be used as the gate width of first transistor (25) and second transistor (24) of Yamakawa ‘237.
But Yamakawa ‘237 as modified by Zang ‘162 fails to explicitly disclose a film thickness of the gate insulating film of the second transistor is smaller than a film thickness of the gate insulating film of the first transistor.
Nevertheless, in a related endeavor (Fig 18-22 of Yorikado ‘232), Yorikado ‘232 teaches a film thickness (thickness of 2057, Fig 19 of Yorikado ‘232, Para [0208]) of the gate insulating film (2057, Fig 21 of Yorikado ‘232, Para [0208]) of the second transistor (2052, fig 21 of Yorikado ‘232, Para [0209]) is smaller than a film thickness (thickness of 1057, Fig 21 of Yorikado ‘232, Para [0208]) of the gate insulating film (1057, Fig 21 of Yorikado ‘232, Para [0208]) of the first transistor (1051, Fig 21 of Yorikado ‘232, Para [0208])(Para [0208 and 0209} of Yorikado ‘232 discloses gate insulating film of second transistor is smaller than gate insulating film of the first transistor)(Note: the feature numbers in Fig 18-21 do not align to the description of the written description paragraphs cited. Examiner has used the feature notation as disclosed in the prior art written description).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Yorikado ‘232’s teaching of a film thickness of the gate insulating film of the second transistor is smaller than a film thickness of the gate insulating film of the first transistor into Yamakawa ‘237 as modified by Zang ‘162’s device. Yamakawa ‘237 as modified by Zang ‘162 discloses an image sensor semiconductor device with multiple FinFET transistors with gate electrodes over the transistors and further teaches a gate width of the source follower transistor (amplification) is larger than the gate width of the row select transistor (select transistor). Yorikado ‘232 teaches a image sensor semiconductor device with multiple transistors and further teaches that the gate insulating film of a transistor can vary in thickness between transistors (Para [0208]). The ordinary artisan would have been motivated to modify Yamakawa ‘237 as modified by Zang ‘162 in the manner set forth above, at least, because as Yorikado ‘232 teaches in Para [0209] when the gate insulating film of a second transistor (second transistor - the amplification transistor) is made thinner the capacitance is increased so the pixel noise can be reduced and further that the greater thickness of the gate insulating film of the first transistor can maintain that transistor’s durability.
As incorporated, the teaching of the insulating film thickness of the second transistor (thickness of 2057) is smaller than the film thickness of the first transistor (thickness of 1057) would be used as the thickness of (251 (insulating film for 25) and 241 (insulating film for 24) of Yamakawa ‘237 as modified by Zang ‘162.
With respect to Claim 3 Yamakawa ‘237 as modified by Zang ‘162 and further modified by Yorikado ‘232 discloses all limitations of the semiconductor device according to claim 1, and Yamakawa ‘237 further discloses wherein each of the first (25) and second field-effect transistors (24) is provided in the same semiconductor (30S, shown in Fig 18)(Fig 20A and Fig 20B and Para [0154] discloses first field effect transistor and second field effect transistor in the same semiconductor 30S).
With respect to Claim 4 Yamakawa ‘237 as modified by Zang ‘162 and further modified by Yorikado ‘232 discloses all limitations of the semiconductor device according to claim 1, and Yamakawa ‘237 further discloses wherein
each of the first (25) and second field-effect transistors (24) further includes a pair of main electrode regions (24B and 25A, Fig 19, Para [0174]) provided in the semiconductor (30S, shown in Fig 18) on both sides of the gate electrode (25G and 24G, Fig 19, Para [0160] in a gate length direction (Y direction, Fig 19), and
the first (24) and second field-effect transistors (25) share one of the pair of main electrode regions (24A/25B, Fig 19, Para [0147] discloses 24 and 25 share source-drain region 24A.25B).
With respect to Claim 6 Yamakawa ‘237 as modified by Zang ‘162 and further modified by Yorikado ‘232 discloses all limitations of the semiconductor device according to claim 1, and Yamakawa ‘237 further discloses wherein
the first field-effect transistor (25) is a switching element (Para [0087] discloses 25 as a selection transistor), and
the second field-effect transistor (24) is an amplification transistor (Para [0087] discloses 24 as an amplification transistor).
With respect to Claim 7 Yamakawa ‘237 as modified by Zang ‘162 and further modified by Yorikado ‘232 discloses all limitations of the semiconductor device according to claim 1, and Yamakawa ‘237 discloses further comprising:
a photoelectric conversion element (21, Fig 3, Para [0087]); and a pixel circuit (P, Fig 1 and 3, Para [0087]) that converts signal charge generated by the photoelectric conversion element as a result of photoelectric conversion into a pixel signal (Examiner’s note: the phrase “that converts signal charge generated by the photoelectric conversion element as a result of photoelectric conversion into a pixel signal” is functional language – manner of operating the device and therefore does not differentiate over the prior art of record. Ref: MPEP § 2114 (II));
wherein the pixel circuit (P) includes an amplification transistor (24) including the second field-effect transistor (Para [0087] discloses 24 as an amplification transistor) and a switching element (25) electrically connected to (24 and 25 electrically connected disclosed in Fig 3 and Para [0087]) the amplification transistor (24) and including the first field-effect transistor (Para [0087] discloses 25 as a selection transistor).
With respect to Claim 8 Yamakawa ‘237 as modified by Zang ‘162 and further modified by Yorikado ‘232 discloses all limitations of the semiconductor device according to claim 7, and Yamakawa ‘237 discloses further comprising: a semiconductor layer (11A, Fig 18, Para [0099]) overlapping the semiconductor (30S) in plan view (Fig 18 and Para [0139] disclose 11 a stacked structure comprising 11A and 30, therefore 11A would overlap 30 (which comprises 30S) in a plan view) and provided with the photoelectric conversion element (21)(Fig 18 and Para [0139] discloses photodiode 21 provided in 11A).
With respect to Claim 9 Yamakawa ‘237 as modified by Zang ‘162 and further modified by Yorikado ‘232 discloses all limitations of the semiconductor device according to claim 1, and Yamakawa ‘237 discloses further wherein one of the first (25) and second field-effect (24) transistors is of a p- channel conductivity type (Para [0100] discloses 24 as p-type channel conductivity) and the other is of an n-channel conductivity type (Para [0156] discloses 25 as n-type channel conductivity).
With respect to Claim 13 Yamakawa ‘237 as modified by Zang ‘162 and further modified by Yorikado ‘232 discloses all limitations of the semiconductor device according to claim 1, but Yamakawa ‘237 as modified by Zang ‘162 and further modified by Yorikado ‘232 fails to expressly disclose wherein a difference in film thickness between the gate insulating film of the first field-effect transistor and the gate insulating film of the second field-effect transistor is 1 nm or more on the upper surface of the semiconductor layer. However, the examiner notes that the applicants disclosure teaches wherein the recited difference between the thickness the gate insulating film has the advantage of suppressing a decrease in reliability of the gate insulating film (Para [0052] of instant application). Having this mind, Yamakawa ‘237 teaches a range of gate insulating film (241) on the field effect transistors having a thickness of 3nm to 15nm (Para [0107]) to provide an insulating film for the transistor channel. Therefore, it would have been obvious to a person of ordinary skill in the art to arrive at the recited limitation through routine optimization, to obtain the well-known advantage of suppressing a decrease in reliability. See MPEP§2144.05 (II)(A),(B).
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With respect to Claim 14 Yamakawa ‘237 discloses an electronic apparatus comprising (Fig 1-7, 18-22H and 30):
a semiconductor device (10A, Fig 30, Para [0219]);
an optical lens (60, Fig 30, Para [0153]) that forms an image of image light from a subject on an imaging plane of the semiconductor device (Examiner’s note: the phrase “that forms an image of image light from a subject on an imaging plane of the semiconductor device” is functional language – manner of operating the device and therefore does not differentiate over the prior art of record. Ref: MPEP § 2114 (II)); and
a signal processing circuit (14, Fig 1, Para [0075]) that performs signal processing on a signal output from the semiconductor layer (Examiner’s note: the phrase “that performs signal processing on a signal output from the semiconductor layer” is functional language – manner of operating the device and therefore does not differentiate over the prior art of record. Ref: MPEP § 2114 (II)) (Note Examiner’s above interpretation of “the semiconductor layer” as “the semiconductor”),
wherein the semiconductor device (10A) includes
first (25, Fig 19, Para [0171]) and second field-effect transistors (24, Fig 19, Para [0171]) for different purposes (Para [0087] discloses 25 as a selection transistor and further discloses 24 as an amplification transistor),
each of the first (25) and second field-effect transistors (24) includes
a channel formation portion (25C (channel for 25) and 24C (channel for 24), Fig 20B and Fig 20A respectively, Para [0172]) provided in a semiconductor (30S around 25C and 24C disclosed in Fig 20B and Fig 20A respectively, Para [0173]) including an upper surface (top of 25C and top of 24C shown in annotated Fig 20A/20B of Yamakawa ‘237) and side surfaces (sides of 25C and side of 24C shown in annotated Fig 20A/20B of Yamakawa ‘237),
a gate electrode (25G and 24G as shown in Fig 20B and 20A respectively, Para [0172]) provided over the upper surface (top of 25C and top of 24C shown in annotated Fig 20A/20B of Yamakawa ‘237) and the side surfaces (sides of 25C and side of 24C shown in annotated Fig 20A/20B of Yamakawa ‘237) in one direction (horizontal direction as shown in annotated Fig 20A/20B of Yamakawa ‘237) of the semiconductor (30S), and
a gate insulating film (251 (insulating film for 25) and 241 (insulating film for 24), Fig 20B and Fig 20A respectively, Para [0172]) provided between the semiconductor (30S) and the gate electrode (25G and 24G)( Fig 20B and 20A disclose gate insulating film provided between semiconductor and gate electrode),
But Yamakawa ‘237 fails to explicitly disclose a width, in the one direction, of the upper surface of the semiconductor layer overlapping the gate electrode of the first transistor is smaller than a width, in the one direction, of the upper surface of the semiconductor layer overlapping the gate electrode of the second transistor, and
Nevertheless, in a related endeavor (Fig 1-2, 4 and 9-11 of Zang ‘162), Zang ‘162 teaches a width (width of 494 as shown in annotated Fig 4 of Zang ‘162, Para [0036]), in the one direction (B2, Fig 4 of Zang ‘162, Para [0036]), of the upper surface of the semiconductor layer (Note Examiner’s above interpretation of “the semiconductor layer” as “the semiconductor”) overlapping the gate electrode of the first transistor (RS404, Fig 4 of Zang ‘162, Para [0036]) is smaller than a width (width of 492 as shown in annotated Fig 4 of Zang ‘162, Para [0036]), in the one direction (B2), of the upper surface of the semiconductor layer (Note Examiner’s above interpretation of “the semiconductor layer” as “the semiconductor”) overlapping the gate electrode of the second transistor (SF402, Fig 4 of Zang ‘162, Para [0036])(Zang ‘162 teaches in Para [0036] “a gate width of source follower gate 492 along axis B2 is larger than a gate width of row-select gate 494, one of ordinary skill in the art would recognize the gate width as the same as the channel width, the upper surface of the channel contacting the gate electrode), and
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Zang ‘162’s teaching of a width, in the one direction, of the upper surface of the semiconductor layer overlapping the gate electrode of the first transistor is smaller than a width, in the one direction, of the upper surface of the semiconductor layer overlapping the gate electrode of the second transistor into Yamakawa ‘237’s device. Yamakawa ‘237 discloses a semiconductor device with multiple finFET transistors with gate electrodes over the transistors and Yamakawa ‘237 and Yamakawa ‘237 discloses a width range for the channel region of one transistor (amplification transistor) but is silent on the channel width of the other transistors (select and reset). Zang ‘162 also teaches a semiconductor device with multiple FinFET transistors with gate electrodes over the transistors and Zang ‘162 further teaches a gate width of the source follower transistor (amplification) is larger than the gate width of the row select transistor (select transistor). The ordinary artisan would have been motivated to modify Yamakawa ‘237 in the manner set forth above, at least, because as Zang ‘162 teaches in Para [0036] that when the gate area of the source follower is greater than the gate area of the row select transistor, the random telegraph noise performance of the transistors can be improved. It would be obvious therefore for one of ordinary skill in the art to increase the gate width of the second transistor to be greater than the gate width of the first transistor as a mechanism to increase the gate area.
As incorporated, the teaching of the gate width of the first transistor (width of 494) being smaller than the gate width of the second transistor (width of 492) would be used as the gate width of first transistor (25) and second transistor (24) of Yamakawa ‘237.
But Yamakawa ‘237 as modified by Zang ‘162 fails to explicitly disclose a film thickness of the gate insulating film of the second transistor is smaller than a film thickness of the gate insulating film of the first transistor.
Nevertheless, in a related endeavor (Fig 18-22 of Yorikado ‘232), Yorikado ‘232 teaches a film thickness (thickness of 2057, Fig 19 of Yorikado ‘232, Para [0208]) of the gate insulating film (2057, Fig 21 of Yorikado ‘232, Para [0208]) of the second transistor (2052, fig 21 of Yorikado ‘232, Para [0209]) is smaller than a film thickness (thickness of 1057, Fig 21 of Yorikado ‘232, Para [0208]) of the gate insulating film (1057, Fig 21 of Yorikado ‘232, Para [0208]) of the first transistor (1051, Fig 21 of Yorikado ‘232, Para [0208])(Para [0208 and 0209} of Yorikado ‘232 discloses gate insulating film of second transistor is smaller than gate insulating film of the first transistor)(Note: the feature numbers in Fig 18-21 do not align to the description of the written description paragraphs cited. Examiner has used the feature notation as disclosed in the prior art written description).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Yorikado ‘232’s teaching of a film thickness of the gate insulating film of the second transistor is smaller than a film thickness of the gate insulating film of the first transistor into Yamakawa ‘237 as modified by Zang ‘162’s device. Yamakawa ‘237 as modified by Zang ‘162 discloses an image sensor semiconductor device with multiple FinFET transistors with gate electrodes over the transistors and further teaches a gate width of the source follower transistor (amplification) is larger than the gate width of the row select transistor (select transistor). Yorikado ‘232 teaches a image sensor semiconductor device with multiple transistors and further teaches that the gate insulating film of a transistor can vary in thickness between transistors (Para [0208]). The ordinary artisan would have been motivated to modify Yamakawa ‘237 as modified by Zang ‘162 in the manner set forth above, at least, because as Yorikado ‘232 teaches in Para [0209] when the gate insulating film of a second transistor (second transistor - the amplification transistor) is made thinner the capacitance is increased so the pixel noise can be reduced and further that the greater thickness of the gate insulating film of the first transistor can maintain that transistor’s durability.
As incorporated, the teaching of the insulating film thickness of the second transistor (thickness of 2057) is smaller than the film thickness of the first transistor (thickness of 1057) would be used as the thickness of (251 (insulating film for 25) and 241 (insulating film for 24) of Yamakawa ‘237 as modified by Zang ‘162.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Yamakawa ‘237 in view of Zang ‘162 in view of Yorikado ‘232 and in further view of Hasegawa et al. (JP 2015204381 A, hereinafter Hasegawa ‘381), in view of the following arguments.
With respect to Claim 2 Yamakawa ‘237 as modified by Zang ‘162 and further modified by Yorikado ‘232 discloses all limitations of the semiconductor device according to claim 1, but Yamakawa ‘237 as modified by Zang ‘162 and further modified by Yorikado ‘232 fails to explicitly disclose wherein the first field-effect transistor and the second field-effect transistor are provided in different semiconductors.
Nevertheless, in a related endeavor (Fig 5 of Hasegawa ‘381), Hasegawa ‘381 teaches wherein the first field-effect transistor (Tsel Fig 5 of Hasegawa ‘381, Para [0040]) and the second field-effect transistor (TSF, Fig 5 of Hasegawa ‘381, Para [0040]) are provided in different semiconductors (Para [0044] and Fig 5 of Hasegawa ‘381 discloses Tsel and TSF provided on different semiconductors (active regions)).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Hasegawa ‘381’s teaching of wherein the first field-effect transistor and the second field-effect transistor are provided in different semiconductors into Yamakawa ‘237 as modified by Zang ‘162 and further modified by Yorikado ‘232’s device. The ordinary artisan would have been motivated to modify Yamakawa ‘237 as modified by Zang ‘162 and further modified by Yorikado ‘232 in the manner set forth above, at least, because as Hasegawa ‘381 teaches in Para [0043], providing the first and second field effect transistors on different semiconductors is advantageous in device layout design.
As incorporated, the teaching of having the first and second field effect transistors on different semiconductors taught by Hasegawa ‘381 would be used as the layout of the first (25) and second (24) field effect transistors of Yamakawa ‘237 as modified by Zang ‘162 and further modified by Yorikado ‘232.
Claims 5 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Yamakawa ‘237 in view of Zang ‘162 in view of Yorikado ‘232 and in further view of Aoki (US 2021/0385397 A1, hereinafter Aoki ‘397), in view of the following arguments.
With respect to Claim 5 Yamakawa ‘237 as modified by Zang ‘162 and further modified by Yorikado ‘232 discloses all limitations of the semiconductor device according to claim 3, but Yamakawa ‘237 as modified by Zang ‘162 and further modified by Yorikado ‘232 fails to explicitly disclose wherein the semiconductor includes a step between the gate electrodes of the first and second field-effect transistors where width in the one direction changes.
Nevertheless, in a related endeavor (Fig 1-5 and 10 of Aoki ‘397), Aoki ‘397 teaches wherein the semiconductor (30, Fig 4 of Aoki ‘397, Para [0061]) includes a step (Fig 10 of Aoki ‘397 discloses a step in the W length between AMP and SEL) between the gate electrodes of the first (AMP, Fig 10 of Aoki ‘397, Para [0092]) and second field-effect transistors (SEL, Fig 10 of Aoki ‘397, Para [0092]) where width in the one direction changes (W length as shown in Fig 10 of Aoki ‘397, Para [0092]).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Aoki ‘397’s teaching of wherein the semiconductor includes a step between the gate electrodes of the first and second field-effect transistors where width in the one direction changes into Yamakawa ‘237 as modified by Zang ‘162 and further modified by Yorikado ‘232’s device. Yamakawa ‘237 as modified by Zang ‘162 and further modified by Yorikado ‘232 discloses an image sensor semiconductor device with multiple FinFET transistors provided on the same semiconductor. Aoki ‘397 teaches a image sensor semiconductor device with multiple transistors and further teaches that semiconductor has a step; a width change in one direction. The ordinary artisan would have been motivated to modify Yamakawa ‘237 as modified by Zang ‘162 and further modified by Yorikado ‘232 in the manner set forth above, at least, because as Aoki ‘397 teaches in Para [0092] this dimensional dimension between the amplification and the selection transistor can lower noise levels of the transistors.
As incorporated, the teaching of the semiconductor includes a step between the gate electrodes of the first and second field-effect transistors where width in the one direction changes of Aoki ‘397 would be used as the shape of the semiconductor (30S) between the first (25) and second (24) field effect transistors of Yamakawa ‘237 as modified by Zang ‘162 and further modified by Yorikado ‘232.
With respect to Claim 10 Yamakawa ‘237 as modified by Zang ‘162 and further modified by Yorikado ‘232 discloses all limitations of the semiconductor device according to claim 1, but Yamakawa ‘237 as modified by Zang ‘162 and further modified by Yorikado ‘232 fails to explicitly disclose wherein a gate length of the second gate electrode is greater than a gate length of the first gate electrode.
Nevertheless, in a related endeavor (Fig 1-5 and 10 of Aoki ‘397), Aoki ‘397 teaches wherein a gate length (W Length, Fig 10 of Aoki ‘397, Para [0092]) of the second gate electrode (AMP, Fig 10 of Aoki ‘397, Para 0092]) is greater than a gate length (length of SEL, as shown Fig 10 of Aoki ‘397, Para [0092]) of the first gate electrode (SEL, Fig 10 of Aoki ‘397, Para [0092]).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Aoki ‘397’s teaching of a gate length of the second gate electrode is greater than a gate length of the first gate electrode into Yamakawa ‘237 as modified by Zang ‘162 and further modified by Yorikado ‘232’s device. Yamakawa ‘237 as modified by Zang ‘162 and further modified by Yorikado ‘232 discloses an image sensor semiconductor device with multiple FinFET transistors provided on the same semiconductor. Aoki ‘397 teaches a image sensor semiconductor device with multiple transistors and further teaches a difference between gate lengths in transistors. The ordinary artisan would have been motivated to modify Yamakawa ‘237 as modified by Zang ‘162 and further modified by Yorikado ‘232 in the manner set forth above, at least, because, as Aoki ‘397 teaches in Para [0092], having a longer gate length on the amplification (second) transistor, “the oxide film capacitance Cox of the amplifier transistor AMP is improved, and the on-resistance R.sub.on of the amplifier transistor AMP is reduced. As a result, … the frequency characteristic of the kTC noise becomes broader, and the noise level becomes lower”.
As incorporated, the teaching of the second gate length being greater than the first gate length of Aoki ‘397 would be used as the gate lengths of the second gate length (gate length of 24) and the first gate length (gate length of 25) of Yamakawa ‘237 as modified by Zang ‘162 and further modified by Yorikado ‘232.
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Yamakawa ‘237 in view of Zang ‘162 in view of Yorikado ‘232 and in further view of Inaba (US 2008/0253170 A1, hereinafter Inaba ‘170) in view of the following arguments.
With respect to Claim 11 Yamakawa ‘237 as modified by Zang ‘162 and further modified by Yorikado ‘232 discloses all limitations of the semiconductor device according to claim 1, but Yamakawa ‘237 as modified by Zang ‘162 and further modified by Yorikado ‘232 fails to explicitly disclose wherein a gate length of the first field-effect transistor is 200 nm or less.
Nevertheless, in a related endeavor (Fig XXX of Inaba ‘170), Inaba ‘170 teaches wherein a gate length (L, Fig 16, Para [0031]) of the first field-effect transistor (MIS FinFET of Para [0031]) is 200 nm or less (Para [0031] discloses a gate length of 30nm).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Inaba ‘170’s teaching of a gate length of the first field-effect transistor is 200 nm or less into Yamakawa ‘237 as modified by Zang ‘162 and further modified by Yorikado ‘232’s device. Yamakawa ‘237 as modified by Zang ‘162 and further modified by Yorikado ‘232 discloses an image sensor semiconductor device with multiple FinFET transistors provided on the same semiconductor but Yamakawa ‘237 as modified by Zang ‘162 and further modified by Yorikado ‘232 fails to explicitly disclose the dimension of the transistor gate lengths. Inaba ‘170 teaches a semiconductor device with multiple transistors and further teaches gate lengths of those transistors. The ordinary artisan would have been motivated to modify Yamakawa ‘237 as modified by Zang ‘162 and further modified by Yorikado ‘232 in the manner set forth above, at least, because as Inaba ‘170 teaches in Para [0031], the cited gate length improves the cut-off characteristic in a short channel region.
As incorporated, the teaching of Inaba ‘170 of a gate length of the first field-effect transistor is 200 nm or less would be used as the gate length of the first field effect transistor (25) of Yamakawa ‘237 as modified by Zang ‘162 and further modified by Yorikado ‘232.
With respect to Claim 12 Yamakawa ‘237 as modified by Zang ‘162 and further modified by Yorikado ‘232 discloses all limitations of the semiconductor device according to claim 1, but Yamakawa ‘237 as modified by Zang ‘162 and further modified by Yorikado ‘232 fails to expressly disclose a difference between a width of the first field-effect transistor on the upper surface of the semiconductor layer and a width of the second field-effect transistor on the upper surface of the semiconductor layer is 10 nm or more. However, the examiner notes that the applicants disclosure teaches wherein the recited width has the advantage of improving the field controllability of a gate (Para [0007] of instant application). Having this mind, (Fig 13-14 of Inaba ‘170), Inaba ‘170 teaches a difference between a width of the first field-effect transistor and a width of the second field-effect transistor. (Para [0130] of Inaba ‘170 teaches the width of a first field effect transistor as 100 nm and in Para [0126] of Inaba ‘170 teaches the width of a second field effect transistor as 50nm) to obtain the advantage of controlling the threshold voltage of the transistors (Para [0133-0134] of Inaba ‘170). Therefore, it would have been obvious to a person of ordinary skill in the art to arrive at the recited limitation through routine optimization, to obtain the well-known advantage of improving the field controllability of a gate. See MPEP§2144.05 (II)(A),(B).
Conclusion
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/PAUL A BERRY/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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