DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Preliminary Amendment
Receipt is acknowledged of the preliminary amendment filed on 07/31/2024.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The disclosure is objected to because of the following informalities: the title is not descriptive. A new title that would include the inventive features of the claimed invention is respectfully requested.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-8 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Aoyama (Pat. No. US 11,300,411) (hereafter Aoyama).
Regarding claim 1, Aoyama teaches a gyro sensor comprising:
a gyro element (i.e., device 100) (see Fig. 1); and
a control unit electrically connected to the gyro element (i.e., physical quantity detection circuit 200) (see Fig. 1),
the gyro element including
a first port to which a drive signal for vibrating the gyro element is applied (i.e., drive circuit 20 generates the drive signal for causing the physical quantity detection device 100 to undergo the excited vibration and supplies the drive electrodes 112 on the physical quantity detection device 100 via the terminal DS) (see Fig. 1),
a second port of outputting a drive sense signal in accordance with the drive signal (i.e., drive circuit 20 receives oscillation current produced at the drive electrodes 113 by the excited vibration of the physical quantity detection device 100 via the terminal DG) (see Fig. 1), and
a third port of outputting a detection signal in accordance with Coriolis force generated at the gyro element (i.e., two detection electrodes 114 and 115 on the physical quantity detection device 100 via the terminals S1 and S2 of the physical quantity detection circuit 200) (see Fig. 1),
the control unit including a drive controller connected to the first port and the second port, the drive controller being configured to generate the drive signal to input to the first port the drive signal generated (i.e., drive circuit 20 generates the drive signal for causing the physical quantity detection device 100 to undergo the excited vibration and supplies the drive electrodes 112 on the physical quantity detection device 100 via the terminal DS) (see Column 6, line 55, to Column 7, line 17), and the drive controller being further configured to feedback-control the drive signal based on the drive sense signal output from the second port (i.e., the drive circuit 20 receives oscillation current produced at the drive electrodes 113 by the excited vibration of the physical quantity detection device 100 via the terminal DG and performs feedback control on the amplitude level of the drive signal in such a way that the amplitude of the oscillation current is held at a fixed value) (see Column 6, line 55, to Column 7, line 17), and
a signal processor connected to the third port, the signal processor being configured to perform signal processing relating to the detection signal output from the third port, the signal processor including
an analog processor to which the detection signal is input (i.e., detection circuit 30 receives the AC charges produced at the two detection electrodes 114 and 115 on the physical quantity detection device 100 via the terminals S1 and S2 of the physical quantity detection circuit 200, respectively, uses the wave-detection signal SDET to detect the physical quantity components contained in the AC charges, and generates and outputs a physical quantity detection signal SAO, which is an analog signal having a voltage level according to the magnitudes of the physical quantity components) (see Column 7, lines 3-17),
an A/D converter configured to convert, into a digital signal, a signal output from the analog processor (i.e., analog/digital conversion circuit 41 operates based on a clock signal ADCLK, converts the physical quantity detection signal SAO, which is an analog signal, into a physical quantity detection signal SDO, which is a digital signal, and outputs the physical quantity detection signal SDO; and analog/digital conversion circuit 42 operates based on the clock signal ADCLK, converts the vibration leakage signal QAO, which is an analog signal, into a vibration leakage signal QDO, which is a digital signal, and outputs the vibration leakage signal QDO) (see Column 7, lines 33-43),
a digital calculator configured to generate an angular velocity signal based on the digital signal output from the A/D converter (i.e., digital signal processing circuit 51 operates based on a master clock signal MCLK, performs predetermined computation on the physical quantity detection signal SDO outputted from the analog/digital conversion circuit 41, and outputs a physical quantity detection signal SDOX provided by the computation; and digital signal processing circuit 52 operates based on the master clock signal MCLK, performs predetermined computation on the vibration leakage signal QDO outputted from the analog/digital conversion circuit 42, and outputs a vibration leakage signal QDOX provided by the computation) (see Column 7 lines 44-55), and
a checker (i.e., failure diagnosis circuit 60) (see Fig. 1),
the analog processor being configured to selectively output either a detection component (i.e., physical quantity detection signal SAO) (see Fig. 1) or
a quadrature component to the A/D converter (i.e., vibration leakage signal QAO) (see Fig. 1),
the detection component and the quadrature component being included in the detection signal,
the checker being configured to check a state relating to the control unit based on a first output signal or a second output signal (i.e., failure diagnosis circuit 60 can therefore diagnose the state of the physical quantity sensor 1 as failure when the magnitude of the vibration leakage signal QDOX generated based on the vibration leakage signal QAO does not fall within the first range) (see Column 7, line 56, to Column 8, line 18),
the first output signal being output from the A/D converter in response to that the quadrature component is input to the A/D converter, and
the second output signal being output from the digital calculator in response to that the first output signal is input to the digital calculator (i.e., failure diagnosis circuit 60 then outputs a failure diagnosis result signal QF representing whether or not the physical quantity sensor 1 has failed) (see Fig. 1).
Regarding claim 2, Aoyama teaches that the checker is configured to make a decision that a malfunction is present in the control unit, when finding that a signal value of the first output signal or the second output signal deviates from a prescribed range at least one time within a predetermine time period (i.e., failure diagnosis circuit 60 can therefore diagnose the state of the physical quantity sensor 1 as failure when the magnitude of the vibration leakage signal QDOX generated based on the vibration leakage signal QAO does not fall within the first range) (see Column 7, line 56, to Column 8, line 18).
Regarding claim 3, Aoyama teaches that the checker is configured to make a decision that a malfunction is present in the control unit, when finding that a specific situation continues over a fixed time, the specific situation being that a signal value of the first output signal or the second output signal deviates from a prescribed range (i.e., failure diagnosis circuit 60 can therefore diagnose the state of the physical quantity sensor 1 as failure when the magnitude of the vibration leakage signal QDOX generated based on the vibration leakage signal QAO does not fall within the first range) (see Column 7, line 56, to Column 8, line 18).
Regarding claim 4, Aoyama teaches that the checker is configured to output, when a checking result of the checker indicates that a malfunction is present, information about presence of the malfunction (i.e., to interface 70) (see Fig. 1).
Regarding claim 5, Aoyama teaches that the analog processor is configured to receive, as a reference signal, the drive signal from the drive controller, and selectively output, based on the reference signal, either the detection component or the quadrature component included in the detection signal (i.e., the drive circuit 20 generates a wave-detection signal SDET having the same phase as that of the drive signal and a wave-detection signal QDET having a phase different by 90° from that of the drive signal and outputs the wave-detection signals SDET and QDET to the detection circuit 30) (see Fig. 1).
Regarding claim 6, Aoyama teaches that the analog processor is configured to receive, as a reference signal, the drive signal from the drive controller, and selectively output, based on the reference signal, either the detection component or the quadrature component included in the detection signal (i.e., the drive circuit 20 generates a wave-detection signal SDET having the same phase as that of the drive signal and a wave-detection signal QDET having a phase different by 90° from that of the drive signal and outputs the wave-detection signals SDET and QDET to the detection circuit 30) (see Fig. 1).
Regarding claim 7, Aoyama teaches that the analog processor is configured to receive, as a reference signal, the drive signal from the drive controller, and selectively output, based on the reference signal, either the detection component or the quadrature component included in the detection signal (i.e., the drive circuit 20 generates a wave-detection signal SDET having the same phase as that of the drive signal and a wave-detection signal QDET having a phase different by 90° from that of the drive signal and outputs the wave-detection signals SDET and QDET to the detection circuit 30) (see Fig. 1).
Regarding claim 8, Aoyama teaches that the analog processor is configured to receive, as a reference signal, the drive signal from the drive controller, and selectively output, based on the reference signal, either the detection component or the quadrature component included in the detection signal (i.e., the drive circuit 20 generates a wave-detection signal SDET having the same phase as that of the drive signal and a wave-detection signal QDET having a phase different by 90° from that of the drive signal and outputs the wave-detection signals SDET and QDET to the detection circuit 30) (see Fig. 1).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: see PTO-892.
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/Tran M. Tran/Examiner, Art Unit 2855
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