Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the Application filed July 6, 2026.
Status of claims to be treated in this office action:
a. Independent: 1, 11
b. Pending: 1-20
Claims 1 and 11 have been amended.
Information Disclosure Statement
The information disclosure statements (IDS) are submitted on 06/10/2026 and 08/18/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The amendments to the Specification have been reviewed and are accepted by
the Examiner. The objections to the Specification are withdrawn.
Claim Rejections - 35 USC § 112
The 112(b) claim rejections are withdrawn pursuant to claim amendments.
Response to Arguments
Applicant's arguments filed July 6, 2026 have been fully considered but they are
not persuasive.
Regarding the 102 rejection of claims 1 and 11 using Balakrishnan, Applicant argues on pp. 7-8 that Balakrishnan’s reference to a precharge command in para. [0030] does not teach “a precharge command to at least one DRAM bank of the particular DRAM bank group to close the at least one DRAM bank”. Examiner does not find this argument persuasive because, per the extended quotation from para. [0030] provided in the updated rejection below, the rank being “removed or blocked from active use” is considered by Balakrishnan to be a first step of the refresh operation, hence “during a refresh operation”. Balakrishnan goes on to describe storing data in a buffer or queue, which is the removal, before the actual refresh step. Further, “during the refresh operation, until each row has been refreshed, the memory controller stores a value from a set of bits in a next row of memory circuits into a row buffer, then precharges the memory circuits of that row of memory circuits, and next writes the stored value from the row buffer back into that row of memory circuits” proves that the precharge occurs before the re-write part of the refresh. Further, “precharge command” is verbiage that can be given its broadest meaning.
Regarding the 102 rejection of claims 1 and 11 using Tan et al, Applicant argues on p. 8 that Tan does not disclose the last two limitations of claims 1 and 11, and the reasoning provided is that Tan does not disclose a system that has a controller that “can intelligently send the precharge command to close the at least one DRAM bank”, nor does Tan send a precharge command “such that individual refresh commands (REFpb) may be issued to the DRAM bank rather than a refresh all command (REFab)”. Examiner does not find these arguments persuasive because claims 1 and 11 do not teach an “intelligent” sending of a precharge command, nor do they teach that the refresh must not eventually be performed on all blocks. It is unclear which claim limitations support the assertion of such “intelligent” command sending.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 11 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Balakrishnan (US Pub. 20200027499 A1).
Regarding independent claim 1, Balakrishnan discloses a memory controller (Fig. 1: memory controller 108; [0019]), comprising:
a refresh scheduler configured to send refresh commands ([0024]: memory controller 108 schedules, causes, and/or controls the performance of refreshes for the DRAM memory circuits in memory functional block 110) to dynamic random-access memory (DRAM) banks of a DRAM memory system comprising DRAM banks arranged in a set of DRAM bank groups each comprising one or more DRAM banks ([0002]: in some electronic devices, DRAM chips on a memory module are included in, or can be operated as, one of N ranks (e.g., 4 ranks, 8 ranks, etc.), with each chip including M banks (e.g., 32 banks) and each bank including a number of arrays of DRAM circuit elements for storing information. Examiner asserts that each rank 124 is analogous to a DRAM bank group because each rank 124 contains multiple banks 122); and
an adaptive precharge scheduler ([0024] per the mapping for the refresh scheduler) configured to:
determine a priority score for each DRAM bank group based on a set of parameters comprising (ii) one or more traffic condition parameters that indicate a characteristic of data traffic for the one or more DRAM bank ([0015]: the criteria relating to the one or more properties of the buffered memory accesses that are used to determine the refresh order include criteria such as a count of buffered memory accesses for each rank (i.e., the total number of memory accesses that are pending in the memory controller for each rank), a type of each of the buffered memory accesses from among a set of types (e.g., reads, writes, moves, deletes, etc.), a priority of the buffered memory accesses from among a set of priorities, etc; [0031]: refresh logic in a memory controller determines an order in which dynamic memory circuits in ranks of memory from among multiple ranks of memory are refreshed. FIG. 2 presents a flowchart illustrating a process for selecting a refresh order to be used for performing refreshes for ranks of memory; also refer to Fig. 2: step 204. Examiner concludes that Balakrishnan teaches determining a priority score for each DRAM bank group based the parameters of type (ii); in other words, Examiner has addressed one limitation (ii) out of two alternatives, and thus has not addressed “(i) one or more status parameters that indicate a status of the one or more DRAM banks”);
select, based on the priority score for each DRAM bank group, a particular DRAM bank group to close ([0003]: in order to refresh a rank, the rank is first removed or blocked from use for performing memory accesses (e.g., reads, writes, etc.), such as by de-asserting a chip availability signal for the DRAM chips in the rank; [0030]: during a refresh operation, a rank of memory to be refreshed is first removed or blocked from active use, so that memory accesses and other operations involving information stored in the memory circuits of the rank of memory are paused, terminated, or otherwise delayed for the duration of the refresh operation. Examiner concludes that “removing” or “blocking” a rank from use is analogous to close a particular DRAM bank group, and that removing/blocking a rank from use occurs before a refresh. Further, as seen below, paras. [0003], [0031], and Fig. 2 demonstrate that there is a priority order, analogous to a priority score, for refreshing the ranks) so that each DRAM bank in the DRAM bank group can be refreshed by the refresh scheduler ([0003]: when performing a refresh operation to recharge circuit elements in DRAM chips, these electronic devices refresh the one or more DRAM chips in ranks as a group; [0031]: refresh logic in a memory controller determines an order in which dynamic memory circuits in ranks of memory from among multiple ranks of memory are refreshed. FIG. 2 presents a flowchart illustrating a process for selecting a refresh order to be used for performing refreshes for ranks of memory); and
send a precharge command to at least one DRAM bank of the particular DRAM bank group to close the at least one DRAM bank ([0030]: during a refresh operation, a rank of memory to be refreshed is first removed or blocked from active use, so that memory accesses and other operations involving information stored in the memory circuits of the rank of memory are paused, terminated, or otherwise delayed for the duration of the refresh operation. For example, in some embodiments, a memory controller stores pending memory access operations in a buffer, queue, or other memory circuit associated with the rank until after the refresh operation is completed. The rank of memory is then refreshed. For example, in some embodiments, for a set of rows of memory elements in a rank, during the refresh operation, until each row has been refreshed, the memory controller stores a value from a set of bits in a next row of memory circuits into a row buffer, then precharges the memory circuits of that row of memory circuits, and next writes the stored value from the row buffer back into that row of memory circuits. Examiner concludes that there is a precharge event involved in the removing/blocking of a rank, and therefore there is a precharge command involved in the removing/blocking of a rank. The command is sent to “a set of rows of memory elements in a rank”, and therefore Examiner concludes that the command is sent to at least one DRAM bank because a bank includes a set of rows).
Independent claim 11 contains the same limitations as claim 1, except for being drafted in method format, and it is thus rejected for the same reasons using Balakrishnan.
Claims 1 and 11 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Tan et al. (CN 112382321 A; “Tan”).
Regarding independent claim 1, Tan discloses a memory controller (Fig. 1: memory controller 100; [0051]), comprising:
a refresh scheduler (refresh control module 107; [0149]) configured to send refresh commands to dynamic random-access memory (DRAM) banks of a DRAM memory system comprising DRAM banks arranged in a set of DRAM bank groups each comprising one or more DRAM banks ([0157]: As shown in Figures 1 and 2, the memory controller 100 is configured to connect to the DRAM and to control the DRAM to refresh. DRAM comprises multiple storage queues, each storage queue comprises multiple block groups, and each block group comprises multiple blocks); and
an adaptive precharge scheduler (pre-charge module 110; [0061]) configured to:
determine a priority score for each DRAM bank group based on a set of parameters comprising at least one of (i) one or more status parameters that indicate a status of the one or more DRAM banks or (ii) one or more traffic condition parameters that indicate a characteristic of data traffic for the one or more DRAM bank ([0093]: the priority order of each level is determined based on block information, which includes at least: whether it is valid, whether it has been refreshed, whether there is a memory access request, whether it is idle, and whether the timing is in accordance with the requirements. Examiner asserts that “whether it has been refreshed” is a status parameter that indicates a status of a block, which is analogous to a DRAM bank, and therefore condition (i) is satisfied. Further, Examiner asserts that “whether there is a memory access request” is a traffic condition parameter, and therefore condition (ii) is also satisfied);
select, based on the priority score for each DRAM bank group, a particular DRAM bank group to close so that each DRAM bank in the DRAM bank group can be refreshed by the refresh scheduler ([0154]: the flag indicates that the refresh request for the second level will wait for the pre-charge module 110 to close the corresponding block or storage queue); and
send a precharge command to at least one DRAM bank of the particular DRAM bank group to close the at least one DRAM bank ([0061]: the pre-charge module 110 will generate a pre-charge command to close the block; also see [0154]).
Independent claim 11 contains the same limitations as claim 1, except for being drafted in method format, and it is thus rejected for the same reasons using Tan.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Balakrishnan (US Pub. 20200027499 A1) as applied to claims 1 and 11 above, and further in view of Miller et al. (US Pub. 20220179556 A1; “Miller”).
Regarding claim 2, Balakrishnan discloses the limitations of claim 1. Balakrishnan discloses a refresh scheduler, but does not disclose:
wherein the refresh scheduler is configured to detect that the at least one DRAM bank is closed and send a refresh command to the at least one DRAM bank in response to detecting that the at least one DRAM bank is closed.
However, Miller teaches:
wherein the refresh scheduler (Fig. 1: on-die refresh control circuitry 120; [0017]: The sideband bus 119 enables the on-die refresh control logic 120 to monitor the host controller-generated command and control signals so that appropriate hidden refresh operations may be scheduled) is configured to detect that the at least one DRAM bank is closed and send a refresh command to the at least one DRAM bank in response to detecting that the at least one DRAM bank is closed ([0031]: one rule that significantly reduces the potential for collisions is to allow hidden refresh operations solely for banks with closed pages and no pending active commands).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Miller to Balakrishnan wherein the refresh scheduler is configured to detect that the at least one DRAM bank is closed and send a refresh command to the at least one DRAM bank in response to detecting that the at least one DRAM bank is closed in order to improve refresh command efficiency and reduce power consumption by managing refresh operations more precisely (Miller, [0011]).
Regarding claim 12, Balakrishnan discloses the limitations of claim 11. Claim 12 contains mostly the same limitations as claim 2, and is thus rejected for the same reasons.
Claims 3 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Balakrishnan (US Pub. 20200027499 A1) and Miller (US Pub. 20220179556 A1) as applied to claims 2 and 12 above, and further in view of Lee (US Pub. 20090150621 A1).
Regarding claim 3, Balakrishnan and Miller together disclose the limitations of claim 2. Balakrishnan does not disclose:
wherein detecting that the at least one DRAM bank is closed comprises receiving, from the adaptive precharge scheduler, data indicating that the at least one DRAM bank is closed.
However, Miller teaches:
detecting that the at least one DRAM bank is closed ([0031])
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Miller to modified Balakrishnan wherein there is a detection that the at least one DRAM bank is closed in order to improve refresh command efficiency and reduce power consumption by managing refresh operations more precisely (Miller, [0011]).
Also, through Lee:
wherein detecting that the at least one DRAM bank ([0013]: The banks of memory 110 are typically banks of dynamic random access memory (DRAM)) is closed comprises receiving, from the adaptive precharge scheduler, data indicating that the at least one DRAM bank is closed ([0016]: In block 250, the controller grants the access request and the component attached to the port can begin reading and writing to the memory. In block 260, the bank access controller provides an indication to components attached to other ports that the bank is reserved and not currently available).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Lee to modified Balakrishnan wherein detecting that the at least one DRAM bank is closed comprises receiving, from the adaptive precharge scheduler, data indicating that the at least one DRAM bank is closed in order to support simultaneous sharing of a multi-port memory device between multiple components with minimal additional hardware (Lee, [0008]).
Regarding claim 13, Balakrishnan and Miller together disclose the limitations of claim 12. Claim 13 contains exactly the same limitations as claim 3, and is thus rejected for the same reasons.
Claims 4 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Balakrishnan (US Pub. 20200027499 A1) as applied to claims 1 and 11 above, and further in view of Fanning (US Pat. 6604186 B1).
Regarding claim 4, Balakrishnan discloses the limitations of claim 1. Balakrishnan does not disclose:
wherein the one or more status parameters for each DRAM bank group comprise a parameter indicating a number of DRAM banks of the DRAM bank group that are open.
However, Fanning teaches:
wherein the one or more status parameters for each DRAM bank group (col. 1, lines 25-27: the memory subsystem is often divided into regions, or banks, accessible through a single "page window") comprise a parameter indicating a number of DRAM banks of the DRAM bank group that are open (col. 1, lines 38-42: Often pages are left open until either a "bank conflict" occurs or the DRAM memory controller becomes unable to track a large number of open pages).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Fanning to modified Balakrishnan wherein the one or more status parameters for each DRAM bank group comprise a parameter indicating a number of DRAM banks of the DRAM bank group that are open in order to implement a page management system to improve data transmission (Fanning, col. 1, lines 33-37).
Regarding claim 14, Balakrishnan discloses the limitations of claim 11. Claim 14 contains exactly the same limitations as claim 4, and is thus rejected for the same reasons.
Claims 5 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Balakrishnan (US Pub. 20200027499 A1) as applied to claims 1 and 11 above, and further in view of Nakagawa (US Pub. 20220319582 A1).
Regarding claim 5, Balakrishnan discloses the limitations of claim 1. Balakrishnan does not disclose:
wherein the one or more traffic condition parameters for each DRAM bank group comprise a number of memory requests received for the DRAM bank group.
However, Nakagawa teaches:
wherein the one or more traffic condition parameters for each DRAM ([0024]: double data rate (DDR) 5 synchronous dynamic random access memory (SDRAM)) bank group comprise a number of memory requests received for the DRAM bank group ([0056]: in the refresh management control circuit 110 according to the present embodiment, when the total number of ACT commands issued to the banks to be managed exceeds the RAAIMT, the RFMab is sent and the RAAIMT is subtracted from the RAA counter; [0078]: the memory access controller performs counting at the RAA counter by using the total number of ACT commands issued to the banks to be managed, and causes an additional refresh command to be issued; [0032]: The ACT command is a command that includes specification of a bank address, a bank group address, and a row address, activates (ACTIVE) a specified bank, and selects a row address. For example, the ACT command causes the bank to transition from an IDLE state to an ACTIVE state).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Nakagawa to modified Balakrishnan wherein the one or more traffic condition parameters for each DRAM bank group comprise a number of memory requests received for the DRAM bank group in order to reduce the amount of circuitry and therefore power consumption involved in refresh management (Nakagawa, [0078]).
Regarding claim 15, Balakrishnan discloses the limitations of claim 11. Claim 15 contains exactly the same limitations as claim 5, and is thus rejected for the same reasons.
Claims 6 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Balakrishnan (US Pub. 20200027499 A1) as applied to claims 1 and 11 above, and further in view of Moon et al. (KR 20160059834 A; “Moon”).
Regarding claim 6, Balakrishnan discloses the limitations of claim 1. Balakrishnan does not disclose:
wherein the one or more traffic condition parameters for each DRAM bank group comprise a number of priority memory requests received for the DRAM bank group.
However, Moon teaches:
wherein the one or more traffic condition parameters for each DRAM bank group comprise a number of priority memory requests received for the DRAM bank group ([0069]: If the number of priority requests exceeds the fourth threshold (N4), the actual operation mode of the corresponding rank is set to normal mode, otherwise the actual operation mode of the corresponding rank is set to low power mode; [0004]: In the case of DRAM, low-power modes include power-down mode and self-refresh mode).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Moon to modified Balakrishnan wherein the one or more traffic condition parameters for each DRAM bank group comprise a number of priority memory requests received for the DRAM bank group in order to reduce power consumption regardless of the number or type of requests (Moon, [0010]).
Regarding claim 16, Balakrishnan discloses the limitations of claim 11. Claim 16 contains exactly the same limitations as claim 6, and is thus rejected for the same reasons.
Claims 7 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Balakrishnan (US Pub. 20200027499 A1) as applied to claims 1 and 11 above, and further in view of Iyer et al. (US Pub. 20130080694 A1; “Iyer”).
Regarding claim 7, Balakrishnan discloses the limitations of claim 1. Balakrishnan does not disclose:
wherein the one or more traffic condition parameters for each DRAM bank group comprise a number of memory request conflicts detected for the DRAM bank group.
However, Iyer teaches:
wherein the one or more traffic condition parameters for each DRAM bank group comprise a number of memory request conflicts detected for the DRAM bank group ([0074]: In some embodiments, the refresh system may adjust its operation depending on the number of conflicts between the memory user and the refresh system).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Iyer to modified Balakrishnan wherein the one or more traffic condition parameters for each DRAM bank group comprise a number of memory request conflicts detected for the DRAM bank group in order to improve memory device density by sharing peripheral circuits between memory banks instead of adding more instances of the peripheral circuits (Iyer, [0039]).
Regarding claim 17, Balakrishnan discloses the limitations of claim 11. Claim 17 contains exactly the same limitations as claim 7, and is thus rejected for the same reasons.
Claims 8 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Balakrishnan (US Pub. 20200027499 A1) as applied to claims 1 and 11 above, and further in view of Meng et al. (CN 102981807 A; “Meng”).
Regarding claim 8, Balakrishnan discloses the limitations of claim 1. Balakrishnan does not disclose:
wherein the one or more traffic condition parameters for each DRAM bank group comprise a number of priority memory request conflicts detected for the DRAM bank group.
However, Meng teaches:
wherein the one or more traffic condition parameters for each DRAM bank group comprise a number of priority memory request conflicts detected for the DRAM bank group ([0075]: The criterion for identifying a shared memory access bottleneck is the proportion of shared memory conflicts; [0093]: If shared memory bank conflicts exist, prioritize resolving them).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Meng to modified Balakrishnan wherein the one or more traffic condition parameters for each DRAM bank group comprise a number of priority memory request conflicts detected for the DRAM bank group in order to reduce memory access bottlenecks by increasing parallelism and to improve task allocation by resolving bank conflicts (Meng, [0023]-[0024]).
Regarding claim 18, Balakrishnan discloses the limitations of claim 11. Claim 18 contains exactly the same limitations as claim 8, and is thus rejected for the same reasons.
Claims 10 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Balakrishnan (US Pub. 20200027499 A1) as applied to claims 1 and 11 above, and further in view of Chishti et al. (US 9001608 B1; “Chishti”).
Regarding claim 10, Balakrishnan discloses the limitations of claim 1. Balakrishnan does not disclose:
wherein the one or more status parameters for each DRAM bank group comprise a refresh status indicating whether the DRAM bank is in a prepone stage, a postpone stage, or is close to a refresh deadline for the DRAM bank.
However, Chishti teaches:
wherein the one or more status parameters for each DRAM bank group comprise a refresh status (col. 1, lines 43-45: Current DRAM devices have the following three operational modes: (1) Active, (2) Power-Down (PD), and (3) Self-refresh (SR); col. 1, lines 60-61: In DDR devices, scheduling of refresh operations is dictated by two timing parameters) indicating whether the DRAM bank is in a prepone stage (col. 6, lines 24-28: FIG. 6 illustrates an embodiment of operations performed by the memory controller 104 to coordinate auto-refresh and self-refresh operations at the memory device. The operations of FIG. 6 may be initiated after processing the expiration of a refresh t.sub.REFI), a postpone stage, or is close to a refresh deadline for the DRAM bank (col. 8, lines 57-62: described embodiments postpone refreshes in a high activity phase and determine an appropriate idle period for refreshing in active mode and switching to self-refresh mode to save power and have the memory module internally initiate refreshes to reduce the postponed refresh count).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Chishti to modified Balakrishnan wherein the one or more status parameters for each DRAM bank group comprise a refresh status indicating whether the DRAM bank is in a prepone stage, a postpone stage, or is close to a refresh deadline for the DRAM bank in order to reduce the time and power needed to refresh a memory rank (Chishti; col. 1, line 67 – col. 2, line 5; col. 2, lines 10-16).
Regarding claim 20, Balakrishnan discloses the limitations of claim 11. Claim 20 contains exactly the same limitations as claim 10, and is thus rejected for the same reasons.
Allowable Subject Matter
Claims 9 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Dong et al. (US Pub. 20150318035 A1): paras. [0007], [0021]- [0022], and [0027]-[0032]; and Figs. 5 and 7 are relevant to claims 1 and 11.
Kim (US Pub. 20170228175 A1): paras. [0012], [0052], [0108], and [0135]; and Figs. 4 and 19 are relevant to claims 1 and 11.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/E.R.A./Examiner, Art Unit 2824
/Richard Elms/ 9/18/26 rteSupervisory Patent Examiner
Art Unit 2824
9/18/2026
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