DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Raynor (US 2006/0108657).
Regarding claim 1, Raynor teaches (FIG. 6):
An island photodiode (201) comprising:
a semiconductor chip (204) having one or more island photodiode regions (208) and one or more carrier collection regions (206),
wherein the one or more island photodiode regions and the one or more carrier collection regions are located in a light receiving area of the semiconductor chip with the one or more of the carrier collection regions being arranged at least partially around each island photodiode region (FIG. 6), and
wherein the one or more carrier collection regions are electrically addressable separately from the one or more island photodiode regions ([0061] – [0072], 232, 230, 266, 268).
Regarding claim 2, Raynor teaches:
The island photodiode as claimed in claim 1, wherein the one or more carrier collection regions are configurable between a carrier collection state in which the one or more carrier collection regions collect carriers generated in the light receiving area and a carrier non-collecting state in which the one or more carrier collection regions do not collect carriers generated in the light receiving area ([0061] – [0072], FIG. 6 – 8).
Regarding claim 3, Raynor teaches:
The island photodiode as claimed in claim 1, wherein each island photodiode region is surrounded by one or more of the carrier collection regions (FIG. 6).
Regarding claim 4, Raynor teaches:
The island photodiode as claimed in claim 1, wherein the one or more carrier collection regions include a carrier collection grid region which extends across the light receiving area, wherein the carrier collection grid region defines one or more grid areas, and wherein each island photodiode region is located in a corresponding grid area (FIG. 11).
Regarding claim 5, Raynor teaches:
The island photodiode as claimed in claim 4, wherein the one or more carrier collection regions include a carrier collection guard ring region which is arranged around the one or more island photodiode regions (FIG. 10).
Regarding claim 6, Raynor teaches:
The island photodiode as claimed in claim 5, wherein each portion of the carrier collection grid region extends from one point on a perimeter of the carrier collection guard ring region to another point on the perimeter of the carrier collection guard ring region (FIG. 10, 11).
Regarding claim 7, Raynor teaches:
The island photodiode as claimed in claim 1, wherein the one or more carrier collection regions are defined by a carrier collection layer which defines one or more apertures in the carrier collection layer, wherein each island photodiode region is located in a corresponding aperture in the carrier collection layer (FIG. 6, [0061] – [0072]).
Regarding claim 8, Raynor teaches:
The island photodiode as claimed in claim 1, wherein each island photodiode region comprises a corresponding doped well region of the semiconductor chip formed in a larger doped well region or a doped substrate of the semiconductor chip, wherein the larger doped well region or the doped substrate is doped with the opposite type of dopant to the dopant or dopants of the one or more island photodiode regions (FIG. 10).
Regarding claim 9, Raynor teaches:
The island photodiode as claimed in claim 1, wherein each carrier collection region comprises a corresponding doped well region of the semiconductor chip formed in a larger doped well region or a doped substrate of the semiconductor chip, wherein the larger doped well region or the doped substrate is doped with the opposite type of dopant to the dopant or dopants of the one or more carrier collection regions (FIG. 10).
Regarding claim 10, Raynor teaches:
The island photodiode as claimed in claim 1, comprising one or more electrically conductive gates, each gate being electrically isolated from a semiconductor material of the semiconductor chip by a layer of electrically insulating material, wherein application of a suitable voltage to one or more of the gates creates one or more of the corresponding carrier collection regions in the semiconductor material of the semiconductor chip in one or more regions of the semiconductor chip underlying the one or more gates ([0048], [0115], CMOS structure taught throughout which inherently includes gate structures).
Regarding claim 11, Raynor teaches:
The island photodiode as claimed in claim 10, wherein each electrically conductive gate comprises, or is formed from, polysilicon ([0048], [0115]).
Regarding claim 12, Raynor teaches ([0055] – [0060]):
The island photodiode as claimed in claim 10, wherein the voltage is selected to create a neutral region or an accumulated region in the one or more corresponding carrier collection regions in the semiconductor material of the semiconductor chip in the one or more regions of the semiconductor chip underlying the one or more gates so as to configure the one or more corresponding carrier collection regions into a non-collecting state or wherein the voltage is selected to create an inverted region or a depletion region in the one or more corresponding carrier collection regions in the semiconductor material of the semiconductor chip in the one or more regions of the semiconductor chip underlying the one or more gates so as to configure the one or more corresponding carrier collection regions into a collecting state.
Regarding claim 13, Raynor teaches (FIG. 11):
The island photodiode as claimed in claim 10, wherein the one or more electrically conductive gates include a gate grid which extends across the light receiving area, wherein the gate grid defines one or more grid areas, and wherein each island photodiode region is located in a corresponding grid area.
Regarding claim 14, Raynor teaches (FIG. 10):
The island photodiode as claimed in claim 10, wherein the one or more carrier collection regions include a carrier collection guard ring region which is arranged around the one or more island photodiode regions.
Regarding claim 15, Raynor teaches (FIG. 10):
The island photodiode as claimed in claim 14, wherein the carrier collection guard ring region comprises a corresponding doped well region of the semiconductor chip formed in a larger doped well region or a doped substrate of the semiconductor chip, wherein the larger doped well region or the doped substrate is doped with the opposite type of dopant to the dopant or dopants of the carrier collection guard ring region.
Regarding claim 16, Raynor teaches (FIG. 11):
The island photodiode as claimed in claim 15, wherein each portion of the gate grid extends from a position overlying one point on a perimeter of the carrier collection guard ring region to a position overlying another point on the perimeter of the carrier collection guard ring region and/or wherein one or more portions of the gate grid extend to a position overlying one or more of the island photodiode regions.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Raynor as applied to claim 1 above, and further in view of Shedletsky et al. (US 2016/0218156).
Regarding claim 17, Raynor fails to expressly disclose:
An electronic device comprising an island photodiode as claimed in claim 1, and a display, wherein the island photodiode is located behind the display and the island photodiode is configured to receive light through the display from a scene located in front of the display and, optionally, wherein the display comprises an OLED display.
However, Shedletsky teaches an electronic device with light sensor structures behind an OLED display.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include the photodiode structure of Raynor in the device of Shedletsky for the predictable advantage of utilizing a conventional light sensor in a conventional manner.
Allowable Subject Matter
Claims 18 – 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art of record fails to teach or fairly render obvious the method of operating a photodiode comprising exposing the light receiving area to first light during a first time period so as to generate carriers in the light receiving area, and collecting, in the one or more carrier collection regions, at least some of the carriers generated in the light receiving area during the first time period so as to cause the collected carriers to flow around a first circuit which includes the one or more carrier collection regions and first external circuitry during the first time period;
interrupting the collection of carriers in the one or more carrier collection regions and exposing the light receiving area to second light during a second time period so as to generate carriers in the light receiving area;
collecting, in the one or more island photodiode regions, at least some of the carriers generated in the light receiving area during the second time period so as to cause a photocurrent to flow around a second circuit which includes the one or more island photodiode regions and second external circuitry during the second time period; and
using the second external circuitry to determine an intensity of the second light incident on the light receiving area during a measurement time period based on a measurement of a quantity representative of the photocurrent flowing around the second circuit through the one or more island photodiode regions during the measurement time period, wherein the measurement time period occurs during the second time period or the measurement time period coincides with the second time period, in combination with other limitations of the claim.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CORY W ESKRIDGE whose telephone number is (571)272-0543. The examiner can normally be reached M - F 9 - 5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CORY W ESKRIDGE/Primary Examiner, Art Unit 2898
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