DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Preliminary Amendment
The preliminary amendment filed on August 05th, 2024 has been entered.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The IDS filed on August 05th, 2024 and February 20th, 2026 have been considered.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Semiconductor device comprising a switching gate and a carrier control gate independently drive from each other and power conversion device using same.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over JP 2004-319624A in view of JP 2019-169575A both cited in the IDS filed on 08/05/2024, English translation included.
In re claim 1, JP 2004-319624A discloses a semiconductor device 10 comprising a switching gate (first IGBT 140) and a carrier control gate (second IGBT 143) that are independently driven from each other, wherein the semiconductor device 10 further includes, in a state where the semiconductor device 10 is viewed in a plan view, a central region cell (region surrounded by second gate pattern 126), a peripheral region cell (region between first gate pattern 125 and the second gate pattern 126) surrounding a whole circumference of the central region cell, and a terminal region (region between the first gate pattern and end of the semiconductor chip) surrounding a whole circumference of the peripheral region cell, the central region cell includes a switching element that has the switching gate 140 and the carrier control gate 143, the peripheral region cell is disposed between the central region cell and the terminal region (see page 5 of English translation and figs. 11-15).
JP 2004-319624A is silent to wherein a gate of a switching element in the peripheral region cell is constituted of only the carrier control gate.
However, JP 2019-169575A discloses in a same field of endeavor, a semiconductor device, including, inter-alia, wherein a gate of a switching element in the peripheral region cell 102 is constituted of only the carrier control gate 22 (see page 3 of English translation and figs. 1, 2, 8, and 9).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by JP 2019-169575A into the semiconductor device of JP 2004-319624A in order to enable wherein a gate of a switching element in the peripheral region cell is constituted of only the carrier control gate in JP 2004-319624A to be formed in order to reduce the amount of carriers accumulated in the peripheral region at the time of turn-off . Furthermore, it would have been obvious because all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the invention. KSR International Co. v. Teleflex Inc. (KSR), 550 U.S. 398 (2007). “If a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond that person’s skill.” Id.
In re claim 2, as applied to claim 1 above, JP 2004-319624A in combination with JP 2019-169575A discloses wherein, an operation state of the semiconductor device 10 has a first state (on state) where a voltage by which an inversion layer is formed in the switching element is applied to the switching gate and the carrier control gate, a second state where a voltage by which the inversion layer is formed in the switching element is applied to the switching gate, and a voltage by which an accumulation layer is formed in the switching element is applied to the carrier control gate; and a third state (carrier control gate turned off) where a voltage by which an accumulation layer is formed in the switching gate is applied to the switching gate and carrier control gate, and in a case where the semiconductor device is shifted from a conduction state to a non-conduction state, the semiconductor device is shifted in an order of the first state, the second state and the third state (see page 4 of English translation and fig. 4A-C of JP 2004-319624A).
In re claim 7, as applied to claim 1 above, JP 2004-319624A in combination with JP 2019-169575A discloses wherein the semiconductor device further comprising a gate pad region 120 disposed adjacently to the peripheral region cell and the terminal region (see page 5 of English translation and fig. 13 of JP 2004-319624A).
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over JP 2004-319624A in view of JP 2019-169575A both cited in the IDS filed on 08/05/2024, as applied to claim 1 above, and further in view of Laven et al. (U.S. Pub. 2015/0091052).
In re claim 3, as applied to claim 1 above, JP 2004-319624A and JP 2019-169575A are silent to wherein, as viewed in a plan view of the semiconductor device, a ratio of a portion where an emitter layer is disposed with respect to the carrier control gate in the peripheral region cell by way of a gate insulation film is smaller than a ratio of a portion where the emitter layer is disposed with respect to the switching gate in the central region cell by way of the gate insulation film.
However, Laven discloses in a same field of endeavor, a semiconductor device, including, inter-alia, wherein, as viewed in a plan view of the semiconductor device, a ratio of a portion where an emitter layer is disposed with respect to the carrier control gate in the peripheral region cell by way of a gate insulation film is smaller than a ratio of a portion where the emitter layer is disposed with respect to the switching gate in the central region cell by way of the gate insulation film (see paragraphs [0039, [0066], [0111] and figs. 1A-B and 13B).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Laven into the semiconductor device of JP 2004-319624A in order to enable wherein, as viewed in a plan view of the semiconductor device, a ratio of a portion where an emitter layer is disposed with respect to the carrier control gate in the peripheral region cell by way of a gate insulation film is smaller than a ratio of a portion where the emitter layer is disposed with respect to the switching gate in the central region cell by way of the gate insulation film in JP 2004-319624A to be formed in order to reduce the length of the emitter region of the switching gate in the peripheral region.
Claim(s) 5 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over JP 2004-319624A in view of JP 2019-169575A, as applied to claim 1 above, and further in view of JP 2012-238715A, all cited in the IDS filed on 08/05/2024, English translation included.
In re claim 5, as applied to claim 1 above, JP 2004-319624A and JP 2019-169575A are silent to wherein, the central region cell, the peripheral region cell and the terminal region have a commonly shared drift layer, and a carrier lifetime killer layer is disposed in the drift layer in the peripheral region cell and in the drift layer in the terminal region.
However, JP 2012-238715A discloses in a same field of endeavor, a semiconductor including, inter-alia, wherein, the central region cell 10, the peripheral region cell 12 and the terminal region have a commonly shared drift layer 30b, and a carrier lifetime killer layer 110 is disposed in the drift layer 30b in the peripheral region cell 12 and in the drift layer in the terminal region (see page 4 of English translation and figs. 10, 14, and 17).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by JP 2012-238715A into the semiconductor device of JP 2004-319624A in order to enable wherein, the central region cell, the peripheral region cell and the terminal region have a commonly shared drift layer, and a carrier lifetime killer layer is disposed in the drift layer in the peripheral region cell and in the drift layer in the terminal region in JP 2004-319624A to be formed in order to obtain a semiconductor device that can reduce switching loss (see English Abstract of JP 2012-238715A).
In re claim 6, as applied to claim 1 above, JP 2004-319624A and JP 2019-169575A are silent to wherein, the central region cell, the peripheral region cell and the terminal region have a commonly shared drift layer, the semiconductor device includes a first carrier injection layer through which carriers are injected in the drift layer in the central region cell, and a second carrier injection layer through which the carriers are injected in the drift layer in the peripheral region cell and the terminal region, and impurity concentration in the second carrier injection layer is low compared to impurity concentration in the first carrier injection layer.
However, JP 2012-238715A discloses in a same field of endeavor, a semiconductor device, including, inter-alia, wherein, the central region cell 10, the peripheral region cell 12 and the terminal region have a commonly shared drift layer 30b, the semiconductor device includes a first carrier injection layer through which carriers are injected in the drift layer in the central region cell, and a second carrier injection layer through which the carriers are injected in the drift layer in the peripheral region cell and the terminal region, and impurity concentration in the second carrier injection layer is low compared to impurity concentration in the first carrier injection layer (see page 4 of English translation and figs. 10, 14, and 17).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by JP 2012-238715A into the semiconductor device of JP 2004-319624A in order to enable wherein, the central region cell, the peripheral region cell and the terminal region have a commonly shared drift layer, the semiconductor device includes a first carrier injection layer through which carriers are injected in the drift layer in the central region cell, and a second carrier injection layer through which the carriers are injected in the drift layer in the peripheral region cell and the terminal region, and impurity concentration in the second carrier injection layer is low compared to impurity concentration in the first carrier injection layer in JP 2004-319624A to be formed in order to obtain a semiconductor device that can reduce switching loss (see English Abstract of JP 2012-238715A).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over JP 2004-319624A in view of JP 2019-169575A, as applied to claim 1 above, and further in view of WO 2018/221032A1, all cited in the IDS filed on 08/05/2024, English translation included
In re claim 10, JP 2004-319264A and JP 2019-169575A are silent to a power conversion device configured to use the semiconductor described in claim 1.
However, WO 2018/221032A1 discloses a power conversion device (power converter 500) using an IGBT having a trench gate shape and two gates (GS, GC) that can be controlled independently (see page 7 of English translation and figs. 1, 4, 5, and 16).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by WO 2018/221032A1 into the semiconductor device of JP 2004-319624A in order to obtain a power conversion device configured to use the semiconductor described in claim 1 in order to reduce the power loss of the IGBT and increasing the efficiency of the power conversion device (see page 2 of English translation of WO 2018/221032A1).
Allowable Subject Matter
Claims 4, 8, and 9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Takahashi (U.S. Pub. 2018/0197853 A1) discloses a semiconductor device 91 comprising a central region cell 81, a peripheral region cell 83 surrounding a whole circumference of the central region cell 81 (see paragraph [0054] and figs. 1-3).
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/KHIEM D NGUYEN/Primary Examiner, Art Unit 2892
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