DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This office action is responding to the amendments filed on 12/04/2025. Claims 1, 3, 17, 19 and 20 have been amended.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4-5, 7, 15-17 and 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lesartre et al. [US 2018/0032400 A1].
Regarding claim 1, Lesartre teaches “A method for performing a periodic task, comprising: determining a time unit, based on a time period needed for scanning a first random access memory, RAM;” as “One memory parameter that logic 106 may adjust is a rate at which memory 102 performs scrub operations.” [¶0018]
“scanning circularly the first RAM; and” as “The data scrub operations may check lines of memory for, and correct any found bit errors.” [¶0018]
“performing a task with a predetermined periodicity, based at least on a cycle number for scanning the first RAM, wherein the task performed with the predetermined periodicity is other than scanning the first RAM;” as “Memory 102 may periodically perform data scrub operations. ” [¶0018] (data scrabbing operation is a memory cleaning operation, which is different operation than just scanning)
“wherein the cycle number is determined, based on the time unit and the predetermined periodicity.” as “a latency of a write cycle,” [¶0028]
Regarding claim 4, Lesartre teaches “wherein the cycle number is stored in a second RAM.” as “When memory 102 is initialized for the first time, logic 106 may assume an initial baseline BER and may set baseline memory parameters. ” [¶0016]
Regarding claim 5, Lesartre teaches “wherein scanning the first RAM comprises: reading a value stored in a memory unit in the first RAM;” as “At block 506, the memory or memory controller may adjust a parameter (e.g. at least one of parameter(s) 108) of the memory based on the determined tolerable BER. In various examples, adjust the parameter may comprise adjusting at least one of a rate of performing data scrub operations, a latency to wait for read signals to stabilize,” [¶0038]
“comparing the value to the cycle number; and incrementing the value, and writing the incremented value to the memory unit, if the value is less than the cycle number.” as “Based on the determination, logic 106 may adjust at least one of memory parameter(s) 108” [¶0017]
Regarding claim 7, Lesartre teaches “wherein the first RAM comprises a plurality of memory units, with each memory unit being used for one task.” as “ Memory 102 comprises a plurality of dies 104A-104N (collectively “dies 104”).” [¶0012]
Regarding claim 15, Lesartre teaches “wherein the first RAM is associated with a field programmable gate array, FPGA, or an application specific integrated circuit, ASIC.” as “Logic 106 may comprise logic, an application-specific integrated circuit (ASIC), firmware, a microcontroller, a field programmable gate array (FPGA), the like, or any combination thereof.” [¶0015]
Regarding claim 16, Lesartre teaches “wherein the task comprises transmitting data packets periodically; or wherein the task comprises transmitting a report periodically: or wherein the task comprises detecting a timeout of a report periodically.” as “Memory controller 302 and memory 102 transmit and receive read and write data via memory interface 304 responsive to read and write requests bound for memory 102.” [¶0026]
Claim 17 is anticipated by Lesartre under the same rationale of anticipation of claim 1.
Claim 19 is anticipated by Lesartre under the same rationale of anticipation of claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2, 8 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lesartre et al. [US 2018/0032400 A1] in view of Lewis et al. [US 7,639, 693 B1].
Claim 2 is rejected over Lesartre and Lewis.
Lesartre does not explicitly teach wherein the time period is needed for scanning a first RAM one time.
However, Lewis teaches “wherein the time period is needed for scanning a first RAM one time.” as “(d) each scheduled destination port poll requires one cycle;” [Col 9, lines 29-30]
Lesartre and Lewis are analogous arts because they teach storage system and memory management.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Lesartre and Lewis before him/her, to modify the teachings of Lesartre to include the teachings of Lewis with the motivation of effective scheduling for a large number of destinations (for example, up to 1 k or more destination loop ports in a particular embodiment) even while allowing different destinations to receive variable length data units. [Lewis, Col 5, lines 20-25]
Claim 8 is rejected over Lesartre and Lewis.
Lesartre does not explicitly teach wherein the plurality of memory units are scanned sequentially or in parallel, during each cycle for scanning the first RAM.
However, Lewis teaches “wherein the plurality of memory units are scanned sequentially or in parallel, during each cycle for scanning the first RAM.” as “(b) parallel processing of a large number (e.g., up to 16 or 32 or more) ports at a time; (c) a scheduler and/or method that can search 1 k or 2 k ports in 64 cycles; (d) each scheduled destination port poll requires one cycle;” [Col 9, lines 25-30]
Lesartre and Lewis are analogous arts because they teach storage system and memory management.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Lesartre and Lewis before him/her, to modify the teachings of Lesartre to include the teachings of Lewis with the motivation of effective scheduling for a large number of destinations (for example, up to 1 k or more destination loop ports in a particular embodiment) even while allowing different destinations to receive variable length data units. [Lewis, Col 5, lines 20-25]
Claim 18 is rejected over Lesartre and Lewis under the same rationale of rejection of claim 2.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lesartre et al. [US 2018/0032400 A1] in view of Zhang et al. [US 9,015,718 B1].
Claim 6 is rejected over Lesartre and Zhang.
Lesartre does not explicitly teach wherein the task is performed, if the value is greater than or equal to the cycle number.
However, Zhang teaches “wherein the task is performed, if the value is greater than or equal to the cycle number.” as “one task can require or use a greater share of the CPU and/or memory than other tasks and can cause the other tasks executed on the computer to have increased task latency or increase the number of CPU cycles needed to complete an instruction.” [Col 1, lines 25-30]
Lesartre and Zhang are analogous arts because they teach storage system and memory management.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Lesartre and Zhang before him/her, to modify the teachings of Lesartre to include the teachings of Zhang with the motivation of overall performance of a task or computer can be improved by identifying tasks that incur severe shared resource contention and cause another task to perform poorly (e.g., an interfering task). [Zhang, Col 2, lines 22-26]
Allowable Subject Matter
Claim 3, 9 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 10-14 are objected as well because they are dependent upon claim 9 which is already objected.
Response to Arguments
Applicant's arguments filed on 12/04/2025 have been fully considered but they are not persuasive. Applicant’s main argument regarding claim 1 and other independent claims is explicitly mentioning “performing a task with a predetermined periodicity, based at least on a cycle number for scanning the first RAM, wherein the task performed with the predetermined periodicity is other than scanning the first RAM;” overcomes the prior art. Examiner respectfully disagrees. Lesartre teaches periodic scanning as well as scrubbing of memory (Ref ¶0018). A scrub operation is by definition is memory cleaning operation, which is significantly more than merely scanning operation. Based on this rationale, rejection to independent claims is still maintained despite the amendment.
Amendments to claims 3 and claim 20 overcomes the previous 101 rejections, therefore those rejections are withdrawn.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MASUD K KHAN whose telephone number is (571)270-0606. The examiner can normally be reached Monday-Friday (8am-5pm).
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/MASUD K KHAN/ Primary Examiner, Art Unit 2132