DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on August 29, 2024, is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Arguments
Applicant's arguments filed May 26, 2026, have been fully considered but they are not persuasive. The alleged common feature of a multilayer logic board having primary and secondary trace layers and traces extending from a common via is taught by Beall, as set forth in the rejection of claim 1. Applicant’s backdrilling/permanent enable or disable argument is not persuasive because that feature is not recited in claim 1 and is not the common feature linking all claims.
Group I, claims 1-11, drawn to a logic board and/or electronic device including a logic board, classified in H05K1/116
Group II, claims 12-15, drawn to a method of fabricating a logic board, classified in at least H05K3/4061 and H05K2203/1543
The groups therefore require different fields of search and do not share a special technical feature over the prior art. Accordingly, the restriction requirement is maintained.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 4 is/are rejected under 35 U.S.C. 102(a)(2) as being unpatentable over Beall et al. (US 4016463 A)
Regarding Claim 1 – Beall teaches a logic board comprising: a plurality of layers (Fig 12), including topmost (Fig 12; 21) and bottommost layers (Fig 12; 30), a primary trace layer (Fig 12; 24 Y signal pattern), and first and second secondary trace layers respectively above and below the primary trace layer; (Fig 12; 23 X signal pattern above primary trace layer 24, and 27 X signal pattern below primary trace layer 24) a conductive via extending from the topmost layer to the bottommost layer (Fig 12; plated through hole 46); a primary conductive trace within the primary trace layer and extending from the conductive via (Fig 8; horizontal lead 79 connected to 46); and first and second selectable secondary conductive traces respectively within the first and second selectable secondary trace layers and extending from the conductive via (Fig 7; vertical lead 77 connected to 46).
Regarding Claim 4 – Beall teaches the logic board of claim 1, wherein the conductive via is a first conductive via, and the logic board further comprises: a second conductive via extending from the topmost and/or bottommost layer to the primary trace layer, the primary conductive trace extending from the first conductive via to the second conductive via (Figs 8, 12; horizontal lead 79 connecting plated through holes 46).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Beall et al. (US 4016463 A)
Regarding Claim 5 – Beall teaches the logic board of claim 4, and teaches or suggests further comprising: a third conductive via extending from the topmost and/or bottommost layer to the first selectable secondary trace layer, the first selectable secondary conductive trace extending from the first conductive via to the third conductive via (Figs 7, 12; plated through holes 46 in first selectable secondary trace layer 23; vertical conducting leads 77 interconnecting plated through holes 46); and a fourth conductive via extending from the topmost and/or bottommost layer to the to the second selectable secondary trace layer, the second selectable secondary conductive trace extending from the first conductive via to the fourth conductive via (Figs 7, 12; plated through holes 46 in second selectable secondary trace layer 27; vertical conducting leads 77 interconnecting plated through holes 46). It would have been obvious to provide Beall’s first and second selectable secondary conductive traces extending from the first conductive via to additional plated through holes 46 in the corresponding first and second selectable secondary trace layers, because Beall teaches using 46 and 77 to interconnect signal paths in the X-signal planes.
Claim(s) 2-3, 6-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Beall et al. (US 4016463 A) in view of Iketani (US 20180279473 A1)
Regarding Claim 2 – Beall teaches the logic board of claim 1, but does not explicitly disclose further comprising: a backdrilled hole at least as large as and concentric with the conductive via, from the topmost layer at least to the first selectable secondary trace layer and not reaching the primary trace layer, resulting in permanent selective enabling of the second selectable secondary conductive trace with respect to conductive connection to the primary conductive trace via the conductive via and permanent selective disabling of the first selectable secondary conductive trace with respect to conductive connection to the primary conductive trace via the backdrilled hole.
Iketani teaches a backdrilled hole at least as large as and concentric with the conductive via (Fig 4; 410, 414; Iketani [0027] states “The backdrilled holes 414 may be larger in diameter than the plated holes 410”), from the topmost layer at least to the first selectable secondary trace layer and not reaching the primary trace layer (Fig 4; 413, 414; Iketani [0027] states “The depth of the backdrilled holes 414 may be dictated by the internal interconnects/traces 413”; see also Fig 6B; 619; Iketani [0038]), resulting in permanent selective enabling of the second selectable secondary conductive trace with respect to conductive connection to the primary conductive trace via the conductive via (Fig 4; 414; Iketani [0027] states “Such backdrilling serves to remove stubs, or portions of the plated hole or vias, that are not needed for signal transmission” and “the part of plated hole/via (i.e., the stub) is no longer than it needs to be”) and permanent selective disabling of the first selectable secondary conductive trace with respect to conductive connection to the primary conductive trace via the backdrilled hole (Fig 6A; 610; Iketani [0035] states “such backdrilling removes both the conductive material and conductive ink along the segment”).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Beall with a backdrilled hole at least as large as and concentric with the conductive via, from the topmost layer at least to the first selectable secondary trace layer and not reaching the primary trace layer, resulting in permanent selective enabling of the second selectable secondary conductive trace with respect to conductive connection to the primary conductive trace via the conductive via and permanent selective disabling of the first selectable secondary conductive trace with respect to conductive connection to the primary conductive trace via the backdrilled hole as taught by Iketani because Iketani [0005] states “these unused via portions result in signal reflections, capacitance, inductance and impedance discontinuities, and signal losses” and [0033] states “Backdrilling the blind plated hole/via results in:… less signal attenuation loss… increased channel bandwidth… reduced parasitic inductance and capacitance”.
Regarding Claim 3 – Beall teaches the logic board of claim 1, but does not explicitly disclose further comprising: a backdrilled hole at least as large as and concentric with the conductive via, from the bottommost layer at least to the second selectable trace layer and not reaching the primary trace layer, resulting in permanent selective enabling of the first selectable secondary conductive trace with respect to conductive connection to the primary conductive trace via the conductive via and permanent selective disabling of the second selectable secondary conductive trace with respect to conductive connection to the primary conductive trace via the backdrilled hole.
Iketani teaches a backdrilled hole at least as large as and concentric with the conductive via (Fig 4; 410, 414; Iketani [0027]), from the bottommost layer at least to the second selectable trace layer and not reaching the primary trace layer (Fig 4; 413, 414; Iketani [0027] states “The depth of the backdrilled holes 414 may be dictated by the internal interconnects/traces 413”; see also Fig 6A; 610; Iketani [0035]), resulting in permanent selective enabling of the first selectable secondary conductive trace with respect to conductive connection to the primary conductive trace via the conductive via and permanent selective disabling of the second selectable secondary conductive trace with respect to conductive connection to the primary conductive trace via the backdrilled hole (Fig 6A; 610; Iketani [0035] states “such backdrilling removes both the conductive material and conductive ink along the segment”).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Beall with a backdrilled hole at least as large as and concentric with the conductive via, from the bottommost layer at least to the second selectable trace layer and not reaching the primary trace layer, resulting in permanent selective enabling of the first selectable secondary conductive trace with respect to conductive connection to the primary conductive trace via the conductive via and permanent selective disabling of the second selectable secondary conductive trace with respect to conductive connection to the primary conductive trace via the backdrilled hole as taught by Iketani because Iketani [0005] states “these unused via portions result in signal reflections, capacitance, inductance and impedance discontinuities, and signal losses” and [0033] states “Backdrilling the blind plated hole/via results in:… less signal attenuation loss… increased channel bandwidth… reduced parasitic inductance and capacitance”.
Regarding Claim 6 – Beall teaches an electronic device comprising: a logic board comprising: a plurality of layers (Fig 12), including topmost (Fig 12; 21) and bottommost layers (Fig 12; 30), a primary trace layer (Fig 12; 24), and first and second secondary trace layers respectively above and below the primary trace layer (Fig 12; 23, 27 respectively); a conductive via extending from the topmost or bottommost layer to the primary trace layer (Fig 12; 46 extending from 21 or 30 to 24); a primary conductive trace within the primary trace layer and extending from the conductive via (Figs 8, 12; horizontal lead 79 connected to 46 in primary trace layer 24); and first and second secondary conductive traces respectively within the first and second secondary trace layers and extending from the conductive via (Figs 7, 12; vertical leads 77 connected to 46on first secondary trace layer 23 and second secondary trace layer 27).
Beall does not explicitly disclose a backdrilled hole at least as large as and concentric with the conductive via, from the bottommost layer at least to the second secondary trace layer and not reaching the primary trace layer, or from the topmost layer at least to the first secondary trace layer and not reaching the primary trace layer.
Iketani teaches a backdrilled hole at least as large as and concentric with the conductive via (Fig 4; 410, 414; Iketani [0027]), from the bottommost layer at least to the second secondary trace layer and not reaching the primary trace layer (Fig 6A; 610; Iketani [0035]), or from the topmost layer at least to the first secondary trace layer and not reaching the primary trace layer (Fig 6B; 619; Iketani [0038]).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Beall with a backdrilled hole at least as large as and concentric with the conductive via, from the bottommost layer at least to the second secondary trace layer and not reaching the primary trace layer, or from the topmost layer at least to the first secondary trace layer and not reaching the primary trace layer as taught by Iketani because Iketani [0005] states “these unused via portions result in signal reflections, capacitance, inductance and impedance discontinuities, and signal losses” and [0033] states “Backdrilling the blind plated hole/via results in:… less signal attenuation loss… increased channel bandwidth… reduced parasitic inductance and capacitance”.
Regarding Claim 7 – Beall in view of Iketani teaches the electronic device of claim 6, wherein the conductive via extends from the topmost layer to the primary trace layer (Beall; Fig 12; 46 extending from 21 to 24) and the backdrilled hole extends from the bottommost layer at least to the second secondary trace layer and not reaching the primary trace layer (Iketani; Fig 6A; 610; Iketani [0035]), wherein the first secondary conductive trace is permanently conductively connected to the primary conductive trace via the conductive via (Beall; Figs 7-8, 12; first secondary trace layer 23, primary trace layer 24, plated through hole 46, vertical conducting leads 77/horizontal lead 79), and the second secondary conductive trace is permanently conductively disconnected from the primary conductive trace via the backdrilled hole (Iketani; Fig 6A; 610; Iketani [0035]).
Regarding Claim 8 – Beall in view of Iketani teaches the electronic device of claim 7, wherein the conductive via is a first conductive via, and the logic board further comprises: a second conductive via extending from the topmost and/or bottommost layer to the first secondary trace layer, the first secondary conductive trace extending from the first conductive via to the second conductive via (Beall; Figs 7, 12; plated through holes 46 in first secondary trace layer 23, vertical conducting leads 77 interconnecting 46), and wherein the electronic device further comprises an electronic component mounted to a top or bottom of the logic board and conductively connected to the second conductive via (Beall; Figs 2-3; LSI chip carrier 13, pads 54, links 58, plated through holes 46).
Regarding Claim 9 – Beall in view of Iketani teaches the electronic device of claim 6, wherein the conductive via extends from the bottommost layer to the primary trace layer (Beall; Fig 12; 46 extending from 30 to 24) and the backdrilled hole extends from the topmost layer at least to the first secondary trace layer and not reaching the primary trace layer (Iketani; Fig 6B; 619; Iketani [0038]), wherein the second secondary conductive trace is permanently conductively connected to the primary conductive trace via the conductive via (Beall; Figs 7-8, 12; 27, 24, 46, 77/79), and the first secondary conductive trace is permanently conductively disconnected from the primary conductive trace via the backdrilled hole (Iketani; Fig 6B; 619; Iketani [0038]).
Regarding Claim 10 – Beall in view of Iketani teaches the electronic device of claim 9, wherein the conductive via is a first conductive via, and the logic board further comprises: a second conductive via extending from the topmost and/or bottommost layer to the second secondary trace layer, the second secondary conductive trace extending from the first conductive via to the second conductive via (Beall; Figs 7, 12; 46 in 27; 77 interconnecting 46), and wherein the electronic device further comprises an electronic component mounted to a top or bottom of the logic board and conductively connected to the second conductive via (Beall; Figs 2-3; 13, 54, 58, 46).
Regarding Claim 11 – Beall in view of Iketani teaches the electronic device of claim 6, wherein the conductive via is a first conductive via, and the logic board further comprises: a second conductive via extending from the topmost and/or bottommost layer to the primary trace layer, the primary conductive trace extending from the first conductive via to the second conductive via (Beall; Figs 8, 12; 79 connecting 46), and wherein the electronic device further comprises an electronic component mounted to a top or bottom of the logic board and conductively connected to the second conductive via (Beall; Figs 2-3; 13, 54, 58, 46).
Conclusion
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/ADITYA SHARMA/Examiner, Art Unit 2847
/TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847
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