DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-13 and 15-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Li et al. (U.S. Publication No. 2022/0013067 A1; hereinafter Li).
With respect to claim 1, Li discloses a display substrate, comprising a plurality of repeating units (see Figures 1 and 4 ¶[0071]), wherein at least one repeating unit comprises at least one first power supply line [VDDL], at least one compensation signal line [SL], at least two data signal line groups [DL] (See Figure 4 and ¶[0075]) and a plurality of sub-pixels (See ¶[0071]), wherein the plurality of sub-pixels form at least two pixel rows and at least two pixel columns (see Figure 1 and 4; repeating unit), and the data signal line group [DL1/DL2 and DL3/DL4] comprises at least two data signal lines; at least one sub-pixel comprises a pixel driving circuit [SPC1], which at least comprises a storage capacitor [Cst] (See Figure 5); the first power supply line and the compensation signal line are arranged between two adjacent pixel columns in the repeating unit (see Figure 4; VSSL, SL and VDDL), and the at least two data signal line groups are arranged on both sides of the repeating unit in a direction of pixel rows, respectively (See Figure 4; DL1/DL2 on one side and DL3/DL4 on the other); and the storage capacitor is arranged between the data signal line and the first power supply line, or the storage capacitor is arranged between the data signal line and the compensation signal line (see Figure 4-5).
With respect to claim 2, Li discloses wherein the repeating unit comprises one compensation signal line [SL] and two first power supply lines which comprise a first one of first power supply lines [VDDL] and a second one of first power supply lines [VSSL], the at least two data signal line groups comprise a first data signal line group and a second data signal line group, and the at least two pixel columns comprise a first pixel column and a second pixel column; the compensation signal line is arranged between the first pixel column and the second pixel column in the repeating unit; the first data signal line group is arranged on a side of the first pixel column away from the compensation signal line, and the second data signal line group is arranged on a side of the second pixel column away from the compensation signal line; the first one of first power supply lines is arranged on a side of the compensation signal line close to the first data signal line group, and the storage capacitor in the first pixel column is arranged between the first data signal line group and the first one of first power supply lines; and the second one of first power supply lines is arranged on a side of the compensation signal line close to the second data signal line group, and the storage capacitor in the second pixel column is arranged between the second data signal line group and the second one of first power supply lines (see Figures 4-5).
With respect to claim 3, Li discloses wherein the at least one repeating unit further comprises two power supply connection electrodes [VDDL/VSSL] (See ¶[0077]), and the power supply connection electrode has a strip shape extending along a direction of the pixel row and is provided across the first pixel column and the second pixel column, wherein one end of the power supply connection electrode is connected to the first one of first power supply lines, and the other end of the power supply connection electrode is connected to the second one of first power supply lines, forming an annular structure for transmitting a first power supply signal within the repeating unit (see Figures 4-6).
With respect to claim 4, Li discloses wherein the at least one repeating unit further comprises a power supply connection electrode (See ¶[0077]), and the power supply connection electrode has a strip shape extending along a direction of the pixel row and is provided across the first pixel column and the second pixel column; and an orthographic projection of the power supply connection electrode on a plane of the display substrate is not overlapped with an orthographic projection of the data signal line on the plane of the display substrate, and the orthographic projection of the power supply connection electrode on the plane of the display substrate is at least partially overlapped with an orthographic projection of the compensation signal line on the plane of the display substrate (see Figures 4-5)
With respect to claim 5, Li discloses wherein the repeating unit comprises one compensation signal line [SL] and one first power supply line [VDDL], the at least two data signal line groups comprise a first data signal line group [DL1/DL2] and a second data signal line group [DL3/DL4], and the at least two pixel columns comprise a first pixel column and a second pixel column; the compensation signal line is arranged between the first pixel column and the second pixel column in the repeating unit, the first data signal line group is arranged on a side of the first pixel column away from the compensation signal line, and the second data signal line group is arranged on a side of the second pixel column away from the compensation signal line; and the first power supply line is arranged on a side of the compensation signal line close to the second data signal line group, the storage capacitor in the first pixel column is arranged between the first data signal line group and the compensation signal line, and the storage capacitor in the second pixel column is arranged between the second data signal line group and the first power supply line (See Figures 4-5).
With respect to claim 6, Li discloses wherein the storage capacitor at least comprises two electrode plates of capacitor; in the first pixel column, there is a first distance between an edge of at least one electrode plate of the capacitor on a side close to the compensation signal line and an edge of the compensation signal line on a side close to the electrode plate of the capacitor, and in the second pixel column, there is a second distance between an edge of at least one electrode plate of the capacitor on a side close to the first power supply line and an edge of the first power supply line on a side close to the electrode plate of the capacitor, wherein the first distance is greater than or equal to the second distance (See Figure 15).
With respect to claim 7, Li discloses wherein the repeating unit comprises one compensation signal line [SL] and one first power supply line [VSSL], the at least two data signal line groups comprise a first data signal line group [DL1/DL2] and a second data signal line group [DL3/DL4], and the at least two pixel columns comprise a first pixel column and a second pixel column; the compensation signal line is arranged between the first pixel column and the second pixel column in the repeating unit, the first data signal line group is arranged on a side of the first pixel column away from the compensation signal line, and the second data signal line group is arranged on a side of the second pixel column away from the compensation signal line; the first power supply line is arranged on a side of the compensation signal line close to the first data signal line group, the storage capacitor in the first pixel column is arranged between the first data signal line group and the first power supply line, and the storage capacitor in the second pixel column is arranged between the second data signal line group and the compensation signal line (see Figure 4-5).
With respect to claim 8, Li discloses wherein the storage capacitor at least comprises two electrode plates of capacitor; in the first pixel column, there is a second distance between an edge of at least one electrode plate of the capacitor on a side close to the first power supply line and an edge of the first power supply line on a side close to the electrode plate of the capacitor, and in the second pixel column, there is a first distance between an edge of at least one electrode plate of the capacitor on a side close to the compensation signal line and an edge of the compensation signal line on a side close to the electrode plate of the capacitor, and the first distance and the second distance are both greater than a distance between an edge of the compensation signal line on a side close to the first power supply line and an edge of the first power supply line on a side close to the compensation signal line (see Figure 15).
With respect to claim 9, Li discloses wherein the repeating unit comprises one first power supply line and two compensation signal lines which comprise a first compensation line and a second compensation signal line, the at least two data signal line groups comprise a first data signal line group and a second data signal line group, and the at least two pixel columns comprise a first pixel column and a second pixel column; the first power supply line is arranged between the first pixel column and the second pixel column in the repeating unit, the first data signal line group is arranged on a side of the first pixel column away from the first power supply line, and the second data signal line group is arranged on a side of the second pixel column away from the first power supply line; the first compensation signal line is arranged on a side of the first power supply close to the first data signal line group, and the storage capacitor in the first pixel column is arranged between the first data signal line group and the first compensation signal line; and the second compensation signal line is arranged on a side of the first power supply line close to the second data signal line group, and the storage capacitor in the second pixel column is arranged between the second data signal line group and the second compensation signal line (See Figure 13).
With respect to claim 10, Li discloses wherein the at least one repeating unit further comprises two compensation connection electrodes, and the compensation connection electrode has a strip shape extending along a direction of the pixel row and is provided across the first pixel column and the second pixel column, wherein one end of the compensation connection electrode is connected to the first compensation signal line, and the other end of the compensation connection electrode is connected to the second compensation signal line, forming an annular structure for transmitting a compensation signal within the repeating unit (see Figure 13)
With respect to claim 11, Li discloses wherein the at least one repeating unit further comprises two compensation connection electrodes, and the compensation connection electrode has a strip shape extending along a direction of the pixel row and is provided across the first pixel column and the second pixel column; and an orthographic projection of the compensation connection electrode on a plane of the display substrate is not overlapped with an orthographic projection of the data signal line on the plane of the display substrate, and the orthographic projection of the compensation connection electrode on the plane of the display substrate is at least partially overlapped with an orthographic projection of the first power supply line on the plane of the display substrate (see Figure 13 and 14)
With respect to claim 12, Li discloses wherein the repeating unit comprises one compensation signal line and one first power supply line, the at least two data signal line groups comprise a first data signal line group and a second data signal line group, and the at least two pixel columns comprise a first pixel column and a second pixel column; the first power supply line is arranged between the first pixel column and the second pixel column in the repeating unit; the first data signal line group is arranged on a side of the first pixel column away from the first power supply line, and the second data signal line group is arranged on a side of the second pixel column away from the first power supply line; the compensation signal line is arranged on a side of the first power supply line close to the second data signal line group, the storage capacitor in the first pixel column is arranged between the first data signal line group and the first power supply line, and the storage capacitor in the second pixel column is arranged between the second data signal line group and the compensation signal line; or the compensation signal line is arranged on a side of the first power supply line close to the first data signal line group, the storage capacitor in the first pixel column is arranged between the first data signal line group and the compensation signal line, and the storage capacitor in the second pixel column is arranged between the second data signal line group and the first power supply line (see Figure 15)
With respect to claim 13, Li discloses wherein the storage capacitor at least comprises two electrode plates of capacitor; in the first pixel column, there is a third distance between an edge of at least one electrode plate of the capacitor on a side close to the first power supply line and an edge of the first power supply line on a side close to the electrode plate of the capacitor, and in the second pixel column, there is a fourth distance between an edge of at least one electrode plate of the capacitor on a side close to the compensation signal line and an edge of the compensation signal line on a side close to the electrode plate of the capacitor; or in the first pixel column, there is a fourth distance between an edge of at least one electrode plate of the capacitor on a side close to the compensation signal line and an edge of the compensation signal line on a side close to the electrode plate of the capacitor, and in the second pixel column, there is a third distance between an edge of at least one electrode plate of the capacitor on a side close to the first power supply line and an edge of the first power supply line on a side close to the electrode plate of the capacitor; and the third distance and the fourth distance are both greater than a distance between an edge of the compensation signal line on a side close to the first power supply line and an edge of the first power supply line on a side close to the compensation signal line (See Figure 15)
With respect to claim 15, Li discloses wherein the storage capacitor comprises a first electrode plate and a second electrode plate, and the pixel driving circuit further comprises a first transistor, a second transistor and a third transistor, wherein a first electrode of the first transistor is connected to the data signal line, a second electrode of the first transistor is connected to the first electrode plate and a gate electrode of the second transistor, respectively, a first electrode of the third transistor is connected to the compensation signal line, and a second electrode of the third transistor is connected to the second electrode plate and a second electrode of the second transistor, respectively; and in the at least one repeating unit, gate electrodes of a plurality of the first transistors and gate electrodes of a plurality of the third transistors are connected to a same scan signal line (See Figure 5 and 15)
With respect to claim 16, Li discloses wherein the first transistor at least comprises a first active layer, a first region of the first active layer is connected to the data signal line through a connection electrode, and a second region of the first active layer is connected to the second electrode plate; and in at least one sub-pixel, an orthographic projection of the first active layer on a plane of the display substrate is not overlapped with an orthographic projection of the data signal line on the plane of the display substrate (See Figure 3 and 5)
With respect to claim 17, Li discloses wherein the third transistor at least comprises a third active layer, a first region of the third active layer is connected to the compensation signal line through a connection electrode, and a second region of the third active layer is connected to the first electrode plate; and in at least one sub-pixel, an orthographic projection of the third active layer on a plane of the display substrate is not overlapped with an orthographic projection of the first power supply line on the plane of the display substrate (See Figure 3 and 5).
With respect to claim 18, Li discloses display apparatus, comprising the display substrate according to claim 1 (see ¶[0013])
With respect to claim 19, Li discloses a method of preparing a display substrate, wherein the display substrate comprises a plurality of repeating units (see Figures 1 and 4 ¶[0071]), and the preparation method comprises: forming at least one first power supply line [VDDL], at least one compensation signal line [SL], at least two data signal line groups [DL1/DL2 and DL3/DL4], and a plurality of sub-pixels (See Figure 4 and ¶[0075]) in at least one repeating unit (See ¶[0071]), wherein the plurality of sub-pixels form at least two pixel rows and at least two pixel columns (see Figure 1 and 4; repeating unit), and the data signal line group comprises at least one data signal line [DL1/DL2 and DL3/DL4]; at least one sub-pixel comprises a pixel driving circuit [SPC1], and the pixel driving circuit at least comprises a storage capacitor [Cst] (See Figure 5); the first power supply line and the compensation signal line are arranged between two adjacent pixel columns in the repeating unit (see Figure 4; VSSL, SL and VDDL), and the at least two data signal line groups are respectively arranged on both sides, in a direction of the pixel rows, of the repeating unit (See Figure 4; DL1/DL2 on one side and DL3/DL4 on the other); and the storage capacitor is arranged between the data signal line and the first power supply line, or the storage capacitor is arranged between the data signal line and the compensation signal line (see Figure 4-5).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li
With respect to claim 14, Li discloses wherein the storage capacitor at least comprises two electrode plate of capacitors, and in at least one pixel column (See Figure 5 and 15), but fails to disclose the distance between an edge of at least one electrode plate of the capacitor on a side close to the compensation signal line and an edge of the compensation signal line on a side close to the electrode plate of the capacitor is greater than or equal to 3 microns.
However, it has been held that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). One of ordinary skill in the art at the time of invention would appreciate that the proper distance between capacitor and the compensation signal line can be established by routine experimentation to eliminate crosstalk or short circuiting between device elements. Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. - Han et al. (U.S. Publication No. 2019/0035874 A1) discloses an OLED display
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONATHAN HAN whose telephone number is (571)270-7546. The examiner can normally be reached 9.00-5.00PM PST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, STEVEN LOKE can be reached at 571-272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JONATHAN HAN/Primary Examiner, Art Unit 2818
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