Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, 5 – 7, 9 – 10, 12 – 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chae ( Pub. No. US 20100258787 A1 ), hereinafter Chae.
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Regarding Independent Claim 1 ( Original ), Chae teaches a transistor comprising:
a graphene layer structure ( Chae, FIG. 2, 110; [0050], graphene channel layer 110) provided on a non-metallic surface of a substrate ( Chae, FIG. 2, 100; [0051], substrate 100 ), the graphene layer structure having an insulating cap ( Chae, FIG. 2, 150; [0051], gate insulation layer 150 );
a source contact ( Chae, FIG. 2, 120; [0051], first electrode 120 ) provided in contact with a first edge ( Chae, FIG. 2, 112; [0052], first region 112 ) of the graphene layer structure ( Chae, FIG. 2, 110 );
an insulator ( Chae, FIG. 2, 130; [0013], interlayer 130; [0014], interlayer may include an insulation layer ) provided in contact with an opposite, second edge ( Chae, FIG. 2, 114; [0052], second region 114 ) of the graphene layer structure ( Chae, FIG. 2, 110 );
a drain contact ( Chae, FIG. 2, 140; [0051], second electrode 140 ) provided in contact with the insulator ( Chae, FIG. 2, 130 ), whereby there is a distance of least separation between the drain contact ( Chae, FIG. 2, 140 ) and the graphene layer structure ( Chae, FIG. 2, 110 ) along the second edge ( Chae, FIG. 2, 114 ) of the graphene layer structure ( Chae, FIG. 2, 110 ) and through the insulator ( Chae, FIG. 2, 130 ); and
a gate contact ( Chae, FIG. 2, 160; [0051], gate electrode 160 ) provided (i) over the graphene layer structure ( Chae, FIG. 2, 110 ) and separated therefrom by the insulating cap ( Chae, FIG. 2, 150 ) and/or (ii) under the graphene layer structure ( Chae, FIG. 2, 110 ) and separated therefrom by substrate ( Chae, FIG. 2, 100 ).
Regarding Claim 3 ( Currently amended ), Chae teaches the transistor as claimed in claim 1, on which this claim is dependent, Chae further teaches:
wherein the insulator ( Chae, FIG. 2, 130 ) is provided as a continuous layer ( Chae, FIG. 2, 150; [0051], gate insulation layer 150 ) over the source ( Chae, FIG. 2, 120 ), the insulating cap ( Chae, FIG. 2, 150 ) and at least a portion of the substrate ( Chae, FIG. 2, 100 ) underlying the drain ( Chae, FIG. 2, 140 ).
Regarding Claim 5 ( Currently amended ), Chae teaches the transistor as claimed in claim 1, on which this claim is dependent, Chae further teaches:
wherein the insulator ( Chae, FIG. 2, 130 ) comprises alumina, silica ( Chae, [0056], The interlayer 130 may include, for example, an oxide … e.g. a silicon oxide ), hafnia, titania, yttria, zirconia and/or yttria-stabilised zirconia.
Regarding Claim 6 ( Currently amended ), Chae teaches the transistor as claimed in claim 5, on which this claim is dependent, Chae further teaches:
wherein the insulator ( Chae, FIG. 2, 130, 150 ) is formed of two sub layers ( Chae, [0057], The gate insulation layer 150 may include an insulation material, e.g. a silicon oxide, a silicon nitride, or a silicon oxinitride. Furthermore, the gate insulation layer 150 may be a multi-layer having a structure in which a silicon oxide and a silicon nitride are stacked, or may be a silicon oxide layer which is partially nitrified ).
Regarding Claim 7 ( Currently amended ), Chae teaches the transistor as claimed in claim 5, on which this claim is dependent, Chae further teaches:
wherein the insulator ( Chae, FIG. 2, 130, 150 ) is formed of three sub layers ( Chae, [0057], the gate insulation layer 150 may be a multi-layer ).
Regarding Claim 9 ( Currently amended ), Chae teaches the transistor as claimed in claim 7, on which this claim is dependent, Chae further teaches:
wherein the insulator ( Chae, FIG. 2, 130, 150 ) is formed of four or more sub-layer ( Chae, [0057], the gate insulation layer 150 may be a multi-layer ).
Regarding Claim 10 ( Currently amended ), Chae teaches the transistor as claimed in claim 1, on which this claim is dependent, Chae further teaches:
wherein the insulating cap ( Chae, FIG. 2, 150 ) comprises alumina, silica, hafnia, titania, yttria, zirconia, yttria-stabilised zirconia, and/or silicon nitride ( Chae, [0057], The gate insulation layer 150 may include an insulation material, e.g. a silicon oxide, a silicon nitride, or a silicon oxinitride. Furthermore, the gate insulation layer 150 may be a multi-layer having a structure in which a silicon oxide and a silicon nitride are stacked, or may be a silicon oxide layer which is partially nitrified ).
Regarding Claim 12 ( Currently amended ), Chae teaches the transistor as claimed in claim 1, on which this claim is dependent, Chae further teaches:
wherein the source contact ( Chae, FIG. 2, 120 ), and optionally one or both of the drain ( Chae, FIG. 2, 140 ) and gate ( Chae, FIG. 2, 160 ) contacts, are metal ( Chae, [0055], Alternatively, the first electrode 120 and the second electrode 140 may include metals ) contacts and/or titanium ( Chae, [0055], titanium (Ti) ) nitride.
Regarding Claim 13 ( Original ), Chae teaches the transistor as claimed in claim 12, on which this claim is dependent, Chae further teaches:
wherein the metal contacts comprise one or more of nickel ( Chae, [0055], nickel (Ni) ) ), chromium, titanium ( Chae, [0055], titanium (Ti) ), aluminium ( Chae, [0055], aluminum (Al) ), platinum ( Chae, [0055], platinum (Pt) ), palladium ( Chae, [0055], palladium (Pd) ), gold ( Chae, [0055], gold (Au) ) and silver.
Regarding Claim 14 ( Currently amended ), Chae teaches the transistor as claimed in claim 12, on which this claim is dependent, Chae further teaches:
wherein the drain contact ( Chae, FIG. 2, 140 ) comprises a further graphene layer structure, or is a metal contact ( Chae, [0055], Alternatively, the first electrode 120 and the second electrode 140 may include metals ).
Regarding Claim 15 ( Currently amended ), Chae teaches the transistor as claimed in claim 12, on which this claim is dependent, Chae further teaches:
wherein the gate contact ( Chae, FIG. 2, 160 ) comprises a further graphene layer structure, or is a metal ( Chae, [0058], The gate electrode 160 may include a conductive material, e.g. poly-silicon or metal. The metal may include at least one of Al, Au, Be, Bi, Co, Cu, Hf, In, Mn, Mo, Ni, Pb, Pd, Pt, Rh, Re, Ru, Ta, Te, Ti, W, Zn, and Zr ) contact, or is a conductive layer under the graphene layer structure separated therefrom by the substrate.
Regarding Claim 16 ( Currently amended ), Chae teaches the transistor as claimed in claim 1, on which this claim is dependent, Chae further teaches:
wherein the non-metallic surface of the substrate ( Chae, FIG. 2, 100 ) is electrically insulative ( Chae, [0053], The substrate 100 may be formed of various materials, e.g. silicon, silicon-germanium, silicon carbide, glass, or plastic. Furthermore, the substrate 100 may include an epitaxial layer, a silicon-on-insulator (SOI) layer, a semiconductor-on-insulator (SEOI) layer, etc. ).
Regarding Independent Claim 17 ( Original ), Chae teaches a method for the manufacture of a transistor, the method comprising:
providing a graphene layer structure ( Chae, FIG. 2, 110; [0050], graphene channel layer 110) having an insulating cap ( Chae, FIG. 2, 150; [0051], gate insulation layer 150 ), on a first region of a non-metallic surface of a substrate ( Chae, FIG. 2, 100; [0051], substrate 100 );
depositing a source contact ( Chae, FIG. 2, 120; [0051], first electrode 120 ) in contact with a first edge ( Chae, FIG. 2, 112; [0052], first region 112 ) of the graphene layer structure ( Chae, FIG. 2, 110 );
forming a continuous layer of an insulator ( Chae, FIG. 2, 130, 150; [0013], interlayer 130; [0014], interlayer may include an insulation layer; [0051], gate insulation layer 150 ) over the source ( Chae, FIG. 2, 120 ), the insulating cap ( Chae, FIG. 2, 150 ) and at least a second region of the substrate adjacent an opposite, second edge ( Chae, FIG. 2, 114; [0052], second region 114 ) of the graphene ( Chae, FIG. 2, 110 );
depositing a drain contact ( Chae, FIG. 2, 140 ) on the continuous layer of insulator ( Chae, FIG. 2, 130, 150 ) over the second region of the substrate, whereby there is a distance of least separation between the drain contact ( Chae, FIG. 2, 140 ) and the graphene ( Chae, FIG. 2, 110 ) layer structure along the second edge ( Chae, FIG. 2, 114 ) of the graphene ( Chae, FIG. 2, 110 ) layer structure and through the insulator ( Chae, FIG. 2, 130, 150 );
optionally forming a further insulating layer ( Chae, FIG. 2, 130, 150 ) over the continuous layer of insulator ( Chae, FIG. 2, 130, 150 ) and the drain contact ( Chae, FIG. 2, 140 ); and
depositing a gate contact ( Chae, FIG. 2, 160; [0051], gate electrode 160 ) on the continuous layer of insulator ( Chae, FIG. 2, 130, 150 ) or, where present, on the further insulating layer ( Chae, FIG. 2, 130, 150 ), over the graphene ( Chae, FIG. 2, 110 ) layer structure and, laterally, relative to the substrate ( Chae, FIG. 2, 100 ), between the source ( Chae, FIG. 2, 120 ) and drain ( Chae, FIG. 2, 140 ) contacts, or, wherein the graphene ( Chae, FIG. 2, 110 ) layer structure having an insulating cap is provided over a gate contact ( Chae, FIG. 2, 160 ), separated therefrom by the substrate ( Chae, FIG. 2, 100 ).
Regarding Claim 18 ( Original ), Chae teaches the method as claimed in claim 17, Chae further teaches:
wherein the graphene ( Chae, FIG. 2, 110 ) layer structure having an insulating cap ( Chae, FIG. 2, 150 ) is provided by evaporation deposition ( Chae, [0054], Alternatively, the graphene channel layer 110 may be formed by using a pyrolysis method for silicon carbide, an extraction method using oxidizers such as hydrazine (NH.sub.2NH.sub.2), or a chemical vapor deposition (CVD) method using a reactant gas including hydrogen and carbon ) of an insulating material through a mask.
Regarding Claim 19 ( Currently amended ), Chae teaches the method as claimed in claim 17, Chae further teaches:
wherein the method further comprises wire bonding a metal ( Chae, [0055], Alternatively, the first electrode 120 and the second electrode 140 may include metals ) wire to the drain contact ( Chae, FIG. 2, 140 ) in the second region.
Regarding Claim 20 ( Currently amended ), Chae teaches the method as claimed in claim 17, Chae further teaches:
wherein the continuous layer of insulator ( Chae, FIG. 2, 130, 150 ) is formed by atomic layer deposition (ALD) ( Chae, [0055], [0058], atomic layer deposition (ALD) ).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2, 4, 11 are rejected under 35 U.S.C. 103 as being unpatentable over Chae, in view of Heo ( Pub. No. US 20130048951 A1 ), herein after Heo.
Regarding Claim 2 ( Original ), Chae teaches the transistor as claimed in claim 1, on which this claim is dependent, Chae further teaches:
wherein the distance of least separation ( Chae, [0056], Furthermore, the interlayer 130 may have a thickness sufficient to cause a tunnelling effect between the graphene channel layer 110 and the second electrode 140 ).
Chae does not explicitly teach:
wherein the distance of least separation is from 1 to 5 nm.
However, Heo teaches:
wherein the distance of least separation is from 1 to 5 nm ( Heo, [0020], A gap between the graphene layer and the first electrode may be in a range from about 1 nm to about 30 nm ).
Chae and Heo are both considered to be analogous to the claimed invention because they are forming field effect transistors having graphene channel layer with tunneling effect. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chae ( [0056], the interlayer 130 may have a thickness sufficient to cause a tunnelling effect between the graphene channel layer 110 and the second electrode 140 ), to incorporate the teachings of Heo ( [0020], A gap between the graphene layer and the first electrode may be in a range from about 1 nm to about 30 nm ), to implement wherein the distance of least separation ( i.e. the thickness or gap or separation between graphene channel and drain ) is from 1 to 5 nm. Doing so would provide specific ranges for the distance of least separation ( i.e. i.e. the thickness or gap or separation between graphene channel and drain ), and therefore cause a tunnelling effect for field effect transistors having graphene channel layer. Furthermore, “ [W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. ” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Regarding Claim 4 ( Original ), Chae teaches the transistor as claimed in claim 3, on which this claim is dependent, Chae further teaches:
wherein the distance of least separation ( Chae, [0056], Furthermore, the interlayer 130 may have a thickness sufficient to cause a tunnelling effect between the graphene channel layer 110 and the second electrode 140 ).
Chae does not explicitly teach:
wherein the distance of least separation is from 1 to 5 nm.
However, Heo teaches:
wherein the distance of least separation is from 1 to 5 nm ( Heo, [0020], A gap between the graphene layer and the first electrode may be in a range from about 1 nm to about 30 nm ).
Chae and Heo are both considered to be analogous to the claimed invention because they are forming field effect transistors having graphene channel layer with tunneling effect. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chae ( [0056], the interlayer 130 may have a thickness sufficient to cause a tunnelling effect between the graphene channel layer 110 and the second electrode 140 ), to incorporate the teachings of Heo ( [0020], A gap between the graphene layer and the first electrode may be in a range from about 1 nm to about 30 nm ), to implement wherein the distance of least separation ( i.e. the thickness or gap or separation between graphene channel and drain ) is from 1 to 5 nm. Doing so would provide specific ranges for the distance of least separation ( i.e. i.e. the thickness or gap or separation between graphene channel and drain ), and therefore cause a tunnelling effect for field effect transistors having graphene channel layer. Furthermore, “ [W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. ” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Regarding Claim 11 ( Currently amended ), Chae teaches the transistor as claimed in claim 1, on which this claim is dependent, Chae further teaches:
wherein the insulating cap ( Chae, FIG. 2, 150 ) has a cross-section.
Chae does not explicitly teach or plot:
wherein the insulating cap has a trapezoidal cross-section.
However, Heo teaches:
wherein the insulating cap ( Heo, FIG. 5, 260; [0085], gate dielectric 260 ) has a trapezoidal ( Heo, FIG. 5, the step of 260 ) cross-section.
Chae and Heo are both considered to be analogous to the claimed invention because they are forming field effect transistors having graphene channel layer with tunneling effect. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chae ( FIG. 2, 150 has two steps ), to incorporate the teachings of Heo ( FIG. 5, the step of 260 form the slope of trapezoidal ), to implement wherein the insulating cap has a trapezoidal cross-section. Doing so would provide specific shape description for the insulating cap having step structure, and therefore it is a description for the step structure of insulating cap for field effect transistors having graphene channel layer.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Chae, in view of Duvall ( Pub. No. US 20110042649 A1 ), herein after Duvall.
Regarding Claim 8 ( Currently amended ), Chae teaches the transistor as claimed in claim 7, on which this claim is dependent, Chae further teaches:
wherein the lowermost and uppermost sub-layers ( Chae, FIG. 2, 130, 150 ), and sandwich a middle sub-layer formed of a different insulator ( Chae, [0057], the gate insulation layer 150 may be a multi-layer ).
Chae does not explicitly teach:
wherein the lowermost and uppermost sub-layers are formed of alumina or zirconia.
However, Duvall teaches:
wherein the lowermost and uppermost sub-layers are formed of alumina or zirconia ( Duvall, [0031], In yet another embodiment of the disclosed thin film transistor, the material of said insulator layer is selected from the group comprising barium strontium titanate, barium zirconate titanate, lead zirconate titanate, lead lanthanum titanate, barium titanate, strontium titanate, barium magnesium fluoride, tantalum pentoxide, titanium dioxid, yttrium trioxide, silicon dioxide (SiO.sub.2), silicon nitride (Si.sub.3N.sub.4), aluminium oxide (Al.sub.2O.sub.3), hafnium oxide (HfO.sub.2), zirconium silicate, hafnium silicate, hafnium silicate oxynitride, titanium oxide, tantalum oxide, alumsilicate, carbon, carbon-doped silicon dioxide, and any combination thereof ).
Chae and Duvall are both considered to be analogous to the claimed invention because they are forming field effect transistors having graphene channel layer with tunneling effect. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chae ( [0057], the gate insulation layer 150 may be a multi-layer ), to incorporate the teachings of Heo ( [0031], insulator layer is selected from the group comprising … barium zirconate titanate, lead zirconate titanate, … aluminium oxide (Al.sub.2O.sub.3) … ), to implement wherein the lowermost and uppermost sub-layers are formed of alumina or zirconia. Doing so would provide specific composites having high dielectric constant for the gate dielectric, and therefore allows thicker layers maintaining high gate capacitance to reduce gate leakage and increases the electric field needed for tunnelling of field effect transistors having graphene channel layer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Da-Wei Lee whose telephone number is 703-756-1792. The examiner can normally be reached M -̶ F 8:00 am -̶ 6:00 pm.
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/DA-WEI LEE/Examiner, Art Unit 2817
/MARLON T FLETCHER/ Supervisory Primary Examiner, Art Unit 2817
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