Prosecution Insights
Last updated: August 06, 2026
Application No. 18/837,664

METALLIZED VIAS IN GLASS AND SILICON SUBSTRATES, INTERPOSERS, AND METHODS FOR PRODUCTION THEREOF

Non-Final OA §102§103
Filed
Aug 12, 2024
Priority
Feb 18, 2022 — provisional 63/311,565 +1 more
Examiner
SHARMA, ADITYA
Art Unit
Tech Center
Assignee
Kuprion Inc.
OA Round
1 (Non-Final)
84%
Grant Probability
Favorable
1-2
OA Rounds
8m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allowance Rate
27 granted / 32 resolved
+24.4% vs TC avg
Strong +21% interview lift
Without
With
+21.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
19 currently pending
Career history
52
Total Applications
across all art units

Statute-Specific Performance

§103
60.8%
+20.8% vs TC avg
§102
30.8%
-9.2% vs TC avg
§112
8.4%
-31.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 32 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statements (IDS) submitted on August 12, 2024, and January 28, 2026, are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1, 6, 8, 10-11, 21 is/are rejected under 35 U.S.C. 102(a)(2) as being unpatentable by over Nolet et al. (WO 2021067330 A2) Regarding Claim 1 – Nolet teaches a metallized substrate (Figs 2A-2B; 20) comprising: a base substrate having one or more vias terminating in the base substrate (Fig 1B; 30), extending between a first face (Fig 2A; 22) and second face of the base substrate (Fig 2A; 24), or any combination thereof, the base substrate comprising a glass substrate or a silicon substrate (Figs 2A-2B; 20; Nolet [0079]); and a via fill material within the one or more vias (Figs 1A-2B; 34, 35, 26; Nolet [0083-0084]), the via fill material comprising: 1) a porous matrix material (Figs 7A-7C, 15A-15B; Nolet [0298-0299]) having a void space of about 30% to about 60% (Figs 7A-7C; Nolet [0129]) and comprising a plurality of electrically conductive particles (Figs 4A, 7A-7B; 62, 62a, 62b); and 2) a conductive network at least partially filling the void space within the porous matrix material (Figs 7A-7B, 15A-15B; 76 in 66), the conductive network comprising a plurality of metal nanoparticles that have been consolidated together with one another (Figs 15A-15B; 62; Nolet [0228, 300-302]). Regarding Claim 6 – Nolet teaches the metallized substrate of claim 1, wherein the electrically conductive particles comprise one or more particles selected from the group consisting of micron-size metal particles, chopped metal filaments, metal nanowires, carbon nanotubes, graphene, a graphite material, and any combination thereof (Figs 4A, 7A; 62; Nolet [0092-0093, 0100] states “electrically conductive particles 62”, “metal, such as copper”, and “1 microns to approximately 10 microns”). Regarding Claim 8 – Nolet teaches the metallized substrate of claim 1, wherein the electrically conductive particles comprise at least micron-size copper particles (Figs 4A, 7A; Nolet [0093, 0100]). Regarding Claim 10 – Nolet teaches the metallized substrate of claim 1, wherein the one or more vias have a diameter up to about 500 microns (Figs 1A-2A; 26, 28, 30, 34; Nolet [0079, 0083-0084] states “10 μm to 25 μm”). Regarding Claim 11 – Nolet teaches the metallized substrate of claim 1, further comprising: one or more conductive traces defined upon at least one of the first face or the second face of the base substrate and in electrical communication with the via fill material (Figs 2A, 17, 18A-18E; 37, 22, 24, 34, 35; Nolet [0086, 0289-0291] states “electrical communication”). Regarding Claim 21 – Nolet teaches an interposer comprising the metallized substrate of claim 1 (Fig 26; interposer 21). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 7, 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nolet et al. (WO 2021067330 A2) Regarding Claim 7 – Nolet teaches the metallized substrate of claim 1, wherein the electrically conductive particles have a diameter no larger than about 1/10th a diameter of the one or more vias, the electrically conductive particles are elongated and have a length no larger than about ¾th of the diameter of the one or more vias, or any combination thereof (Figs 1B, 4A, 7A-7B; 26, 34, 62a-c, 66; Nolet [0079, 0100, 0104-0106, 0115] states “10 μm to 25 μm”, “1 micron to approximately 10 microns”, “0.01 micron to approximately 1 micron” and particles 76 “fit in… the interstices 66”). It would have been obvious to select Nolet’s smaller disclosed particles for Nolet’s vias to improve fit/packing within the via. Regarding Claim 9 – Nolet teaches the metallized substrate of claim 8, wherein the metal nanoparticles comprise copper nanoparticles (Figs 4A-4C, 7B; 62a-b, 76; Nolet [0092, 0102, 0106, 0233] states “metal, such as copper”, “second particles 62b can include any suitable electrically conductive material”, “0.01 micron to approximately 1 micron”, and “same metal can be copper”). It would have been obvious to use copper for Nolet’s metal nanoparticles because Nolet teaches nanoscale second particles and teaches the first and second particles may be the same metal, including copper. Claim(s) 2, 3, 5, 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nolet et al. (WO 2021067330 A2) and in further view of Danforth et al. (US 4365003 A) Regarding Claim 2 – Nolet teaches metallized substrate of claim 1, but does not explicitly disclose wherein the electrically conductive particles are bonded together with a cured silicate-reactive matrix material, wherein the silicate-reactive matrix material cures at a temperature within a range of room temperature to about 100° C. Danforth teaches the electrically conductive particles are bonded together with a cured silicate-reactive matrix material, wherein the silicate-reactive matrix material cures at a temperature within a range of room temperature to about 100° C (Danforth states “water soluble silicates including sodium”, “an aqueous based sodium silicate is preferred”, “cured silicate topcoating”, and “210° F”). It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Nolet with the electrically conductive particles are bonded together with a cured silicate-reactive matrix material, wherein the silicate-reactive matrix material cures at a temperature within a range of room temperature to about 100° C as taught by Danforth to provide Nolet’s electrically cured silicate material to bind and stabilize the conductive particle matrix at low temperature. Regarding Claim 3 – Nolet in view of Danforth teaches the metallized substrate of claim 2, wherein the cured silicate-reactive matrix material comprises a cured liquid glass binder (Danforth states “water soluble silicates including sodium”, “an aqueous based sodium silicate is preferred”, and “cured silicate topcoating”). Regarding Claim 5 – Nolet in view of Danforth teaches the metallized substrate of claim 2, wherein the cured silicate-reactive matrix material is also chemically bonded to a wall surface of the one or more vias (Danforth states “water soluble silicates including sodium”, “an aqueous based sodium silicate is preferred”, “cured silicate topcoating”, and curing makes the topcoating “water resistant”). Regarding Claim 22 – Nolet in view of Danforth teaches an interposer comprising the metallized substrate of claim 2 (Nolet; Fig 26; interposer 21; Danforth as applied to claim 2 teaches the cured silicate reactive matrix material/cure limitation). Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nolet et al. (WO 2021067330 A2) in view of Danforth et al. (US 4365003 A) and in further view of Iwasa (US 4735676 A) Regarding Claim 4 – Nolet in view of Danforth teaches the metallized substrate of claim 2, but does not explicitly disclose wherein a mass ratio of the electrically conductive particles to the cured silicate-reactive matrix material in the via fill material ranges from about 6:1 to about 30:1. Iwasa teaches a mass ratio of the electrically conductive particles to the cured silicate-reactive matrix material in the via fill material ranges from about 6:1 to about 30:1 (Iwasa teaches copper powder of about 80-85% by weight and binder/resin of about 15-20% by weight, providing a conductive particle to binder ratio close to about 6:1). It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Nolet in view of Danforth with a mass ratio of the electrically conductive particles to the cured silicate-reactive matrix material in the via fill material ranges from about 6:1 to about 30:1 as taught by Iwasa to increase electrical conductivity of the via fill material while retaining sufficient cured matrix material to bind the electrically conductive particles together. Claim(s) 15, 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nolet et al. (WO 2021067330 A2) and in further view of Len et al. (US 20210227695 A1) Regarding Claim 15 – Nolet teaches the metallized substrate of claim 1. Nolet does not explicitly disclose a printed circuit board comprising the metallized substrate or a plurality of metallized substrates that are stacked upon one another. Len teaches a printed circuit board comprising filled vias (Figs 1A, 3A-3B; 104, 106A-G, plated or filled vias; Len [0008, 0010] states “a printed circuit board (PCB) assembly”, “a PCB comprising a plurality of layers”, and “106A-G may be filled with copper or other via fill materials”). It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Nolet with the printed circuit board as taught by Len to use Nolet’s metallized vias substrate in a PCB assembly for high-density electrical interconnection. Regarding Claim 19 – Nolet in view of Len teaches the printed circuit board of claim 15, wherein one or more conductive traces are defined upon at least one of the first face or the second face of the base substrate and in electrical communication with the via fill material (Nolet; Figs 17-18B; 37, 22/24, 34, 35; Nolet [0289] states “the redistribution layer 37 can be applied to one or both of the first and second surfaces 22 and 24… so as to be in electrical communication with the via 34”; Len; Figs 1A, 10A; 104, traces; Len [0010, 0125] states “a PCB comprising… traces”, and “traces can be added to any layer within the PCB”). Claim(s) 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nolet et al. (WO 2021067330 A2) in view of Len et al. (US 20210227695 A1) and in further view of Danforth et al. (US 4365003 A) Regarding Claim 16 – Nolet in view of Len teaches the printed circuit board of claim 15, but does not explicitly disclose wherein the electrically conductive particles are bonded together with a cured silicate-reactive matrix material, wherein the silicate-reactive matrix material cures at a temperature within a range of about room temperature to about 100° C. Danforth teaches the electrically conductive particles are bonded together with a cured silicate-reactive matrix material, wherein the silicate-reactive matrix material cures at a temperature within a range of about room temperature to about 100° C (Danforth states “water soluble silicates including sodium”, “an aqueous based sodium silicate is preferred”, “cured silicate topcoating”, and “210° F”). It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Nolet in view of Len with the electrically conductive particles are bonded together with a cured silicate-reactive matrix material, wherein the silicate-reactive matrix material cures at a temperature within a range of about room temperature to about 100° C as taught by Danforth to provide Nolet’s electrically cured silicate material to bind and stabilize the conductive particle matrix at low temperature. Regarding Claim 17 – Nolet in view of Len and Danforth teaches the printed circuit board of claim 16, wherein one or more conductive traces are defined upon at least one of the first face or the second face of the base substrate and in electrical communication with the via fill material (Nolet; Figs 17-18B; 37, 22/24, 34, 35; Nolet [0289]; Len; Figs 1A, 10A; 104, traces; Len [0010, 0125]). Claim(s) 12-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nolet et al. (WO 2021067330 A2) in view of Cupta et al. (US 4718993 A) and in further view of Reuter et al. (US 4051094 A) Regarding Claim 12 – Nolet teaches the metallized substrate of claim 11, wherein the one or more conductive traces directly contact the via fill material or indirectly contact the via fill material by way of a bonding pad (Figs 17-18B; 37, 34, 35; Nolet [0289]), but does not explicitly disclose wherein the one or more conductive traces are located upon a seed layer adhered to at least one of the first face or the second face of the base substrate, the seed layer being electrically conductive and comprising a cured silicate-reactive matrix material and a second plurality of electrically conductive particles mixed with the cured silicate-reactive matrix material. Cupta teaches the one or more conductive traces are located upon a seed layer adhered to at least one of the first face or the second face of the base substrate (printed wiring board through holes/surfaces; Cupta states “a dried deposit containing carbon black is left in the holes and on other exposed surfaces” and the board is then placed in an electroplating bath for copper coating), the seed layer being electrically conductive (Cupta states the carbon black-covered board is dried to leave “a dried deposit containing carbon black” in the holes and exposed surfaces, and the board is then electroplated with copper). It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Nolet with the one or more conductive traces are located upon a seed layer adhered to at least one of the first face or the second face of the base substrate, the seed layer being electrically conductive as taught by Cupta because Cupta’s seed/deposit layer would provide a conductive foundation for forming Nolet’s traces and improve electrical continuity between the traces and via fill material. Reuter teaches the seed layer comprising a cured silicate-reactive matrix material (Figs 2-3; 5; Reuter states “potassium or sodium silicate”, “drying… approximately 90° C”, and “silicates solution, serves to bond the electrically conductive particles”) and a second plurality of electrically conductive particles mixed with the cured silicate-reactive matrix material (Reuter states “aqueous plastics dispersion containing the electrically conductive particles”). It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Nolet with the seed layer comprising a cured silicate-reactive matrix material and a second plurality of electrically conductive particles mixed with the cured silicate-reactive matrix material as taught by Reuter because Nolet uses conductive particle based metallization and Reuter’s silicate reactive matrix material would bond and stabilize the conductive particles at low temperature while maintaining seed layer conductivity. Regarding Claim 13 – Noelt in view of Cupta and Reuter teaches the metallized substrate of claim 12, but does not explicitly disclose wherein the seed layer has a thickness ranging from about 1 micron to about 30 microns. Cupta teaches a conductive copper layer thickness about the claimed range (Cupta states “deposited copper layer on each through hole wall is about 1±0.2 mil thick”). It would have been obvious to use Cupta’s conductive layer thickness for the seed layer of Nolet to provide a sufficiently conductive foundation for conductive trace formation. Regarding Claim 14 – Nolet in view of Cupta and Reuter teaches the metallized substrate of claim 12, wherein the second plurality of electrically conductive particles in the seed layer comprises micron-size metal particles, metal nanoparticles, or any combination thereof (Reuter states “electrically conductive particles”, “particles having a noble metal surface”, “silver-coated copper powder”, and “potassium silicate solution”). Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nolet et al. (WO 2021067330 A2) in view of Len et al. (US 20210227695 A1) and Danforth et al. (US 4365003 A) and in further view of Cupta et al. (US 4718993 A) and Reuter et al. (US 4051094 A) Regarding Claim 18 – Nolet in view of Len and Danforth teaches the printed circuit board of claim 17, but does not explicitly disclose wherein the one or more conductive traces are located upon a seed layer adhered to at least one of the first face or the second face of the base substrate, the seed layer being electrically conductive and comprising a cured silicate-reactive matrix material and a second plurality of electrically conductive particles mixed with the cured silicate-reactive matrix material. Cupta teaches the one or more conductive traces are located upon a seed layer adhered to at least one of the first face or the second face of the base substrate (printed wiring board through holes/surfaces; Cupta states “a dried deposit containing carbon black is left in the holes and on other exposed surfaces” and the board is then placed in an electroplating bath for copper coating), the seed layer being electrically conductive (Cupta states the carbon black-covered board is dried to leave “a dried deposit containing carbon black” in the holes and exposed surfaces, and the board is then electroplated with copper). It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Nolet in view of Len and Danforth with the one or more conductive traces are located upon a seed layer adhered to at least one of the first face or the second face of the base substrate, the seed layer being electrically conductive as taught by Cupta because Cupta’s seed/deposit layer would provide a conductive foundation for forming Nolet’s traces and improve electrical continuity between the traces and via fill material. Reuter teaches the seed layer comprising a cured silicate-reactive matrix material (Figs 2-3; 5; Reuter states “potassium or sodium silicate”, “drying… approximately 90° C”, and “silicates solution, serves to bond the electrically conductive particles”) and a second plurality of electrically conductive particles mixed with the cured silicate-reactive matrix material (Reuter states “aqueous plastics dispersion containing the electrically conductive particles”). It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Nolet in view of Len and Danforth with the seed layer comprising a cured silicate-reactive matrix material and a second plurality of electrically conductive particles mixed with the cured silicate-reactive matrix material as taught by Reuter because Nolet uses conductive particle based metallization and Reuter’s silicate reactive matrix material would bond and stabilize the conductive particles at low temperature while maintaining seed layer conductivity. Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nolet et al. (WO 2021067330 A2) and Len et al. (US 20210227695 A1) and in further view of Cupta et al. (US 4718993 A) and Reuter et al. (US 4051094 A) Regarding Claim 19 – Nolet in view of Len teaches the printed circuit board of claim 17, but does not explicitly disclose wherein the one or more conductive traces are located upon a seed layer adhered to at least one of the first face or the second face of the base substrate, the seed layer being electrically conductive and comprising a cured silicate-reactive matrix material and a second plurality of electrically conductive particles mixed with the cured silicate-reactive matrix material. Cupta teaches the one or more conductive traces are located upon a seed layer adhered to at least one of the first face or the second face of the base substrate (printed wiring board through holes/surfaces; Cupta states “a dried deposit containing carbon black is left in the holes and on other exposed surfaces” and the board is then placed in an electroplating bath for copper coating), the seed layer being electrically conductive (Cupta states the carbon black-covered board is dried to leave “a dried deposit containing carbon black” in the holes and exposed surfaces, and the board is then electroplated with copper). It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Nolet in view of Len with the one or more conductive traces are located upon a seed layer adhered to at least one of the first face or the second face of the base substrate, the seed layer being electrically conductive as taught by Cupta because Cupta’s seed/deposit layer would provide a conductive foundation for forming Nolet’s traces and improve electrical continuity between the traces and via fill material. Reuter teaches the seed layer comprising a cured silicate-reactive matrix material (Figs 2-3; 5; Reuter states “potassium or sodium silicate”, “drying… approximately 90° C”, and “silicates solution, serves to bond the electrically conductive particles”) and a second plurality of electrically conductive particles mixed with the cured silicate-reactive matrix material (Reuter states “aqueous plastics dispersion containing the electrically conductive particles”). It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Nolet in view of Len with the seed layer comprising a cured silicate-reactive matrix material and a second plurality of electrically conductive particles mixed with the cured silicate-reactive matrix material as taught by Reuter because Nolet uses conductive particle based metallization and Reuter’s silicate reactive matrix material would bond and stabilize the conductive particles at low temperature while maintaining seed layer conductivity. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADITYA SHARMA whose telephone number is (571)270-7246. The examiner can normally be reached Monday - Friday 8:30 - 5:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at (571) 272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ADITYA SHARMA/Examiner, Art Unit 2847 /TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847
Read full office action

Prosecution Timeline

Aug 12, 2024
Application Filed
Aug 12, 2024
Response after Non-Final Action
Jul 16, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
84%
Grant Probability
99%
With Interview (+21.1%)
2y 7m (~8m remaining)
Median Time to Grant
Low
PTA Risk
Based on 32 resolved cases by this examiner. Grant probability derived from career allowance rate.

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