Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the limitation “wherein the redistribution layer chip further includes a through-electrode that is located in a through-hole that is formed in the first mold resin layer” of claim 12 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 12,19 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 12, it is not clear as to how “wherein the redistribution layer chip further includes a through-electrode that is located in a through-hole that is formed in the first mold resin layer” is being met. Redistribution layer chip does not show any through-electrode. Proper correction is requested.
Regarding claim 19, it is not clear as to how an intermediate stage of fabricating a redistribution layer chip with temporary substrate (38M, para 192) be considered as a device claim. Proper modification/correction is requested.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
1. Claim(s) 1,4-10,15,17,20 is/are rejected under 35 U.S.C. 102a(1) as being anticipated by JP 2018093162 A (Jung).
Regarding claim 1, Jung shows (Fig. 9) a semiconductor package (100A, para 60) comprising:
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an interposer (110, para 51);
a redistribution layer chip (122, para 80) adjacent to the interposer; and
a semiconductor element (181,191, para 78) that overlaps the interposer and the redistribution layer chip, wherein the redistribution layer chip includes a redistribution element (124a,124b,124c) that has a surface overlapping the semiconductor element and a first mold resin layer (123, para 53) that is mounted to an opposite surface of the redistribution element and that contains resin, the opposite surface being opposite the surface of the redistribution element overlapping the semiconductor element, wherein the redistribution element includes an insulating layer (124a, para 53) that has an insulation property and a first redistribution layer (124b+124c, para 53) that is covered by the insulating layer, and the first redistribution layer includes a first conductive portion (124c) that is at least partly located on the surface of the redistribution element overlapping the semiconductor element, wherein the interposer includes a second redistribution layer (142, para 67) that includes a second conductive portion (142) that is located on a surface of the interposer overlapping the semiconductor element, and wherein the semiconductor element (181 or 191) is electrically connected to the first conductive portion and the second conductive portion (para 43).
Regarding claim 4, Jung shows (Fig. 9) wherein a linear expansion coefficient of the first mold resin layer (123, polyimide, 20 ppm /°C (or K)) is lower than a linear expansion coefficient of the insulating layer (124a, photoimageable dielectric PID, 40 ppm/°C).
Regarding claim 5, Jung shows (Fig. 9) wherein a Young's modulus of the first mold resin layer (123, polyimide, 2.5 GPa) is more than a Young's modulus of the insulating layer (124a, photoimageable dielectric PID, 1 GPa).
Regarding claim 6, Jung shows (Fig. 9) wherein bending stiffness of the first mold resin layer is more than bending stiffness of the insulating layer (based on reading above for claim 6).
Regarding claim 7, Jung shows (Fig. 9) wherein a thickness of the first mold resin layer (123 thickness around 122) is more than a thickness of the insulating layer (124a).
Regarding claim 8, Jung shows (Fig. 9) wherein the first mold resin layer (123) contains a particulate filler that is dispersed in the resin (para 56).
Regarding claim 9, Jung shows (Fig. 9) wherein thermal conductivity of the filler is more than thermal conductivity of the resin (epoxy resin, para 56).
Regarding claim 10, Jung shows (Fig. 9) wherein the filler is composed of an inorganic material (silica, para 56).
Regarding claim 15, Jung shows (Fig. 9) wherein the resin (123) that is contained in the first mold resin layer is at least epoxy resin (para 56), polyimide, acryl resin, bismaleimide, polybenzoxazole, or benzocyclobutene.
Regarding claim 17, Jung shows (Fig. 9) a redistribution layer chip (122, para 80) comprising:
a redistribution element(124a,124b,124c) that includes an insulating layer (124a, para 53) having an insulation property and a redistribution layer (124b+124c, para 53) covered by the insulating layer and that has a first surface (top) and a second surface (bottom) opposite the first surface, the redistribution layer including a conductive portion (124b, para 53) that is at least partly located at the first surface; and
a mold resin layer (123, para 53) that is mounted to the second surface and that contains resin.
Regarding claim 20, Jung shows (Fig. 9) a method of manufacturing a semiconductor package, the method comprising:
a step of placing a redistribution layer chip (122, para 80) adjacent to an interposer (110, para 51); and
a step of mounting a semiconductor element (181,191, para 78) that overlaps the interposer and the redistribution layer chip, wherein the redistribution layer chip includes a redistribution element (124a,124b,124c) that has a surface overlapping the semiconductor element and a first mold resin layer (123, para 53) that is mounted to an opposite surface of the redistribution element and that contains resin, the opposite surface being opposite the surface of the redistribution element overlapping the semiconductor element,
wherein the redistribution element includes an insulating layer (124a, para 53) that has an insulation property and a first redistribution layer (124b+124c, para 53) that is covered by the insulating layer, the first redistribution layer includes a first conductive portion that is at least partly located on the surface of the redistribution element overlapping the semiconductor element, and the interposer includes a second redistribution layer (142, para 67) that includes a second conductive portion that is located on a surface of the interposer overlapping the semiconductor element, and wherein at the step of mounting the semiconductor element, the semiconductor element is electrically connected to the first conductive portion and the second conductive portion (para 43).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
1. Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jung, as applied to claim 1 above further in view of US 20230148143 A1 (Lee).
Regarding claim 2, Jung shows the semiconductor element with the interposer and the redistribution layer chip interposed therebetween.
Jung does not show further comprising: a support carrier that faces the semiconductor element with the interposer and the redistribution layer chip interposed therebetween and that supports the interposer and the redistribution layer chip,
wherein the support carrier is separable from the interposer and the redistribution layer chip.
Lee shows (Fig. 13-14) support carrier (900, para 110) is separable.
It would have been obvious to one of ordinary skill in the art, at or before the effective filing date of the invention was made, to add the invention of Lee, with support carrier, to the invention of Jung.
The motivation to do so is that the combination produces the predictable result of building the interposer and the redistribution layer chip on a carrier substrate to reduce any warping during fabrication.
2. Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jung, as applied to claim 1 above further in view of US 20210134728 A1 (Rubin).
Regarding claim 3, Jung shows the interposer, the redistribution layer chip and the semiconductor element.
Jung does not show further comprising: a second mold resin layer that covers the interposer and the redistribution layer chip, that is mounted to the interposer and the redistribution layer chip, and that holds the semiconductor element.
Rubin shows (Fig. 3E) further comprising: a second mold resin layer (170, para 53) that covers the interposer (610) and the redistribution layer chip (110), that is mounted to the interposer and the redistribution layer chip, and that holds the semiconductor element (140 or 150).
It would have been obvious to one of ordinary skill in the art, at or before the effective filing date of the invention was made, to add the invention of Rubin, with second mold resin, to the invention of Jung.
The motivation to do so is that the combination produces the predictable result of protecting the semiconductor element sides and the interposer and redistribution layer chip below.
3. Claim(s) 11,13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jung, as applied to claim 1.
Regarding claim 11, Jung shows the filler in resin.
Jung does not show wherein color of the filler is black.
When the semiconductor compound recited in the reference is substantially identical to that of the claims, claimed properties or functions (eg. Color) are presumed to be inherent. Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 195 USPQ 430, 433 (CCPA 1977).
Regarding claim 13, Jung shows the first conductive portion includes a first wiring, and the second conductive portion includes a second wiring.
Jung does not show wherein a line width of the first wiring is less than a line width of the second wiring.
Line widths of wirings are based on the current carrying requirements. Thus, it would have been obvious to one of ordinary skill in the art at the time the invention was made to select a known wire width on the basis of its suitability for the intended use as a matter of obvious design choice, In re Leshin, 125 USPQ 416 (CCPA 1960).
Regarding claim 14, Jung shows the first conductive portion includes a first wiring.
Jung does not show a line width of the first wiring is 10 μm or less.
Line widths of wirings are based on the current carrying requirements. Thus, it would have been obvious to one of ordinary skill in the art at the time the invention was made to select a known wire width on the basis of its suitability for the intended use as a matter of obvious design choice, In re Leshin, 125 USPQ 416 (CCPA 1960).
4. Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jung, as applied to claim 1 above further in view of US 20220375866 A1 (Pietambaram).
Regarding claim 12, Jung shows the redistribution layer chip and the first mold resin layer.
Jung does not show the redistribution layer chip further includes a through-electrode that is located in a through-hole that is formed in the first mold resin layer.
Pietambaram shows (Fig. 1) the redistribution layer chip (300, para 34) further includes a through-electrode (308, para 34).
It would have been obvious to one of ordinary skill in the art, at or before the effective filing date of the invention was made, to add the invention of Pietambaram, with through-electrode, to the invention of Jung.
The motivation to do so is that the combination produces the predictable result of having pathway for stack interconnection between the two ends of the chip.
5. Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jung in view of Lee.
Regarding claim 16, Jung shows (Fig. 9) a semiconductor package intermediate comprising:
an interposer (110);
a redistribution layer chip (122) adjacent to the interposer; and
wherein the redistribution layer chip includes a redistribution element (124a,124b,124c) and a mold resin layer (123) that is mounted to the redistribution element and that contains resin,
wherein the redistribution element includes an insulating layer (124a) that has an insulation property and a first redistribution layer (124b+124c) that is covered by the insulating layer, the first redistribution layer includes a first conductive portion (124b, 124c) that is at least partly located on a surface opposite a surface of the redistribution element to which the mold resin layer is mounted, and the interposer includes a second redistribution layer (142) that includes a second conductive portion (142) that is located on a surface opposite a surface that faces the support carrier substrate.
Jung does not show a support carrier substrate that supports the interposer and the redistribution layer chip,
wherein the redistribution layer chip is mounted to the support carrier substrate with the mold resin layer connected to the support carrier substrate,
wherein the support carrier substrate is separable from the interposer and the redistribution layer chip.
Lee shows (Fig. 13-14) support carrier (900, para 110) is separable.
It would have been obvious to one of ordinary skill in the art, at or before the effective filing date of the invention was made, to add the invention of Lee, with support carrier, to the invention of Jung.
The motivation to do so is that the combination produces the predictable result of building the interposer and the redistribution layer chip on a carrier substrate to reduce any warping during fabrication.
6. Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jung, as applied to claim 17 above, further in view of US 20180182801 A1 (Tan).
Regarding claim 18, Jung shows the mold resin layer.
Jung does not show further comprising: an adhesive layer that is mounted to a surface opposite a surface of the mold resin layer that is mounted to the second surface, wherein the adhesive layer has heat-sensitive adhesiveness, or photosensitive adhesiveness, or pressure-sensitive adhesiveness.
Tan shows (Fig. 3b) an adhesive layer (140, para 49) below the chip (180, para 49).
Jung in combination with Tan teaches the whole limitation.
It would have been obvious to one of ordinary skill in the art, at or before the effective filing date of the invention was made, to add the invention of Tan, with adhesive layer, to the invention of Jung.
The motivation to do so is that the combination produces the predictable result of avoiding warpage due to heat (para 49).
Allowable Subject Matter
Claim 21 is allowed.
Regarding claim 21, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “a step of mounting, to the support carrier substrate, a redistribution layer chip adjacent to the interposer, wherein the redistribution layer chip includes a redistribution element and a mold resin layer that is mounted to the redistribution element and that contains resin, and the redistribution layer chip is mounted to the support carrier substrate with the mold resin layer connected to the support carrier substrate” when taken in combination with all the remaining limitations of the independent claim.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WASIUL HAIDER whose telephone number is (571)272-1554. The examiner can normally be reached M-F 9 a.m. - 6 p.m..
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/WASIUL HAIDER/Primary Examiner, Art Unit 2812
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