DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Morris et al. (20200075609).
As to claim 1, Morris discloses a storage device comprising: a memory cell comprising a transistor and a capacitor (Fig. 5, [0037], [0072] – [0073]); and
a conductor (Fig. 5, [0037], [0072] – [0073]),
wherein the transistor comprises a source electrode, a drain electrode, and a first gate electrode (Fig. 5, [0037], [0044], [0072] – [0073]),
wherein the capacitor comprises a first electrode, a dielectric over the first electrode, and a second electrode over the dielectric (Fig. 5, [0037], [0044], [0072] – [0073]),
wherein a top surface and a side surface of one of the source electrode and the drain electrode of the transistor are in contact with the conductor (Fig. 5, [0037], [0044], [0072] – [0073]),
wherein a top surface of the other of the source electrode and the drain electrode of the transistor is in contact with the first electrode of the capacitor (Fig. 5, [0037], [0072] – [0073]), and
wherein the dielectric comprises a ferroelectric material (Fig. 5, [0017], [0037], [0151], [0174]).
As to claim 2, Morris teaches the storage device according to claim 1, wherein the dielectric of the capacitor comprises hafnium, zirconium, and oxygen ([0021], [0070], [0177]).
As to claim 3, Morris teaches the storage device according to claim 1, wherein the dielectric of the capacitor comprises aluminum, scandium, and nitrogen ([0021], [0070], [0177]).
As to claim 4, Morris teaches the storage device according to any one of claim 1, wherein the transistor comprises an oxide semiconductor ([0063], [0070]).
As to claim 5, Morris teaches the storage device according to claim 1, wherein the transistor further comprises a second gate insulator and a second gate electrode (Fig. 5, [0037]),
wherein a top surface of the second gate insulator of the transistor is in contact with part of the other of the source electrode and the drain electrode of the transistor (Fig. 5, [0037]), and
wherein the second gate electrode of the transistor overlaps with the first gate electrode of the transistor with the second gate insulator of the transistor therebetween (Fig. 5, [0037], [0073]).
As to claim 6, Morris teaches the storage device according to claim 1, comprising: a plurality of layers each comprising the memory cell and the conductor, wherein the plurality of layers are stacked, and wherein the conductors in the plurality of layers overlap with each other (Fig. 5, [0072] – [0073]).
As to claims 7-12, it is the apparatus of claims 1-6. Please see claims 1-6 for detail analysis.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AFROZA Y CHOWDHURY whose telephone number is (571)270-1543. The examiner can normally be reached M-F 9am-5pm.
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/AFROZA CHOWDHURY/Primary Examiner, Art Unit 2628
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