DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed on August 15, 2024.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on August 15, 2024, September 5, 2025, December 8, 2025 is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Treatment Method of Power Semiconductor Module to Improve Gate Oxide Deterioration.
Claim Objections
Claim 1 is objected to because of the following informalities: Lines 4, 6, 8, and 12 recite a “.” after each subsequent “a”, “b”, “c”, and “d”. For purposes of examination this will be interpreted to have a “:” instead.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1, lines: 2-3 recite the limitation “a Metal-Oxide-Semiconductor element and/or a Metal-Insulator-Semiconductor element…” It is unclear whether the treatment method includes both a metal-oxide-semiconductor element and a metal-insulator-semiconductor element or if it includes one of the two. For purposes of examination this will be interpreted as “a Metal-Oxide-Semiconductor element or a Metal-Insulator-Semiconductor element…”
Claim 10, lines: 6-8 recite the limitation “the ON-state gate voltage Vcc is decreased with respect to a previous value of the ON-state gate voltage Vcc and/or the OFF-state gate voltage VEE” It is unclear if the ON-state gate voltage is decreased with respect to the ON-state gate voltage, the OFF-state gate voltage or if it is decreased with respect with both. For purposes of examination this will be interpreted as “the ON-state gate voltage Vcc is decreased with respect to a previous value of the ON-state gate voltage Vcc or the OFF-state gate voltage VEE”
Claim 11, line 3 recite the limitation “the delay time of the turn-off tOFF is further dependent from the ON-state gate voltage Vcc and/or the OFF-state gate voltage…” It is unclear whether the delay time is dependent from the ON-state gate voltage, from the OFF-state gate voltage or if it is dependent from both. For purposes of examination this will be interpreted as “the delay time of the turn-off tOFF is further dependent from the ON-state gate voltage Vcc or the OFF-state gate voltage…”
Claim 13 recites the limitation "the software" in line 2. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination this will be interpreted as “the computer software”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-9 and 11-14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Spessot (US 2015/0171857). Claim 1, Spessot discloses (Figs. 1-4) a treatment method of a power semiconductor module comprising at least one semiconductor element including a Metal-Oxide-Semiconductor element or a Metal-Insulator-Semiconductor element, said method comprising (method concerns OSS phenomenon for MOSFETs, Para [0006] – [0008]): a: acquiring a first value Vsoh,0 (Fig. 2, 26, Vth value is established, Par a[0086]) corresponding to an initial state of health of a gate oxide of the module (26 shows initial health of gate oxide); b: acquiring a second value Vsoh,X (Fig. 12, 12, determining step of change of Vth, Para [0069]) corresponding to a current state of health of a gate oxide of the module (12 checks OSS degradation, Para [0069]); c: deducing an ON-state gate voltage Vcc or an OFF-state gate voltage VEE, and a delay time of the turn-on toN or a delay time of the turn-off tOFF in function of said acquired first value Vsoh,0 and said second value Vsoh,X (Fig. 2, 12 shoes a step of determining the duration of the off state or not withing the tolerance, Para [0072] – [0074]); d: generating at least one control signal configured to apply the deduced gate voltage Vcc or VEE to the module during the deduced delay time tON or tOFF (Fig. 2, 15, restoration signal applied of voltage pulse with a predetermined duration for gate voltage, Para [0074] – [0076]).
Claim 2, Spessot discloses (Figs. 1-4) the method according to claim 1, further comprising the following preliminary operation: - switching said at least one semiconductor element * from an ON-state to an OFF-state, according to a control logic signal with a zero or negative gate voltage VEE and with a delay time for the turning-off tOFF; or * from an OFF-state to an ON-state, according to a control logic signal with a positive gate voltage Vcc and with a delay time for the turning-on toN ((Fig. 2, 15 a restoration signal is applied to reach the threshold voltage reverting back to ON-state, the signal has a vgate pulse with a determined duration (Para [0072] – [0076]. Claim 3, Spessot discloses (Figs. 1-4) the method according to claim 1, wherein the sign of the applied gate voltage Vcc or VEE depends on the ON/OFF state of said at least one semiconductor element (Fig. 4 and table 1 shows the different gate biases based on the threshold needed, Para [0090] – [0098]). Claim 4, Spessot discloses (Figs. 1-4) the method according to claim 1, wherein (Fig. 3) criteria to deduce the delay time of the turn-on ton or the delay time of the turn-off tOFF in function of said acquired first value Vsoh,0 and said acquired second value Vsoh,X includes the following: - if the acquired second value Vsoh,X is superior to the acquired first value Vsoh,0, the delay time of the turn-off tOFF is increased with respect to a previous value of the delay time of the turn-off tOFF (16 is the conditional test to see if Vth is lower or higher than Vth after the test and a bias may be applied and time tOFF would be increased, Para [0088], see also Fig. 4) ; - if the acquired second value Vsoh,X is inferior to the acquired first value Vsoh,0, the delay time of the turn-off tOFF is decreased with respect to a previous value of the delay time of the turn-off tOFF (16 is the conditional test to see if Vth is lower or higher than Vth after the test and a bias may be applied and time tOFF would be decreased, Para [0088], see also Fig. 4).
Claim 5, Spessot discloses (Figs. 1-4) the method according to claim 1, wherein criteria to deduce the ON-state gate voltage Vcc or an OFF-state gate voltage VEE in function of said acquired first value Vsoh,0 and said acquired second value Vsoh,X includes the following: - if the acquired second value Vsoh,X is superior to the acquired first value Vsoh,0, the ON-state gate voltage Vcc is increased with respect to a previous value of the ON-state gate voltage Vcc, and the increasing is proportional or equal to the difference between the acquired first value Vsoh,0 and the acquired second value Vsoh,X (if a positive shift in Vth is detected a positive voltage may be applied to counteract the negative difference, Para [0077]).
Claim 6, Spessot discloses (Figs. 1-4) the method according to claim 1, wherein criteria to deduce the ON-state gate voltage Vcc or an OFF-state gate voltage VEE in function of said acquired first value Vsoh,0 and said acquired second value Vsoh,X includes the following: - if the acquired second value Vsoh,X is superior to the acquired first value Vsoh,0, the OFF-state gate voltage VEE is decreased with respect to a previous value of the OFF-state gate voltage VEE; - if the acquired second value Vsoh,X is inferior to the acquired first value Vsoh,0, the OFF-state gate voltage VEE is increased with respect to a previous value of the OFF-state gate voltage VEE (if change of Vth is negative then a restoration signal in the positive is applied, Para [0070] – [0071]); - if the acquired second value Vsoh,X is equal to the acquired first value Vsoh,0, the OFF-state gate voltage VEE is maintained equal to a previous value of the OFF-state gate voltage VEE.
Claim 7, Spessot discloses (Figs. 1-4) the method according to claim 1, wherein criteria to deduce the ON-state gate voltage Vcc or an OFF-state gate voltage VEE in function of said acquired first value Vsoh,0 and said acquired second value Vsoh,X includes the following: - if the acquired second value Vsoh,X is superior to the acquired first value Vsoh,0, the OFF-state gate voltage VEE is decreased with respect to a previous value of the OFF-state gate voltage VEE; - if the acquired second value Vsoh,X is inferior to the acquired first value Vsoh,0, the ON-state gate voltage Vcc is increased with respect to a previous value of the ON-state gate voltage Vcc (if change of Vth is negative then a restoration signal in the positive is applied, Para [0070] – [0071]); - if the acquired second value Vsoh,X is equal to the acquired first value Vsoh,0, the ON-state gate voltage Vcc and the OFF-state gate voltage VEE are each reinitialized to their respective value by default.
Claim 8, Spessot discloses (Figs. 1-4) the method according to claim 1, further comprising the following operation: - when a reverse conduction of the semiconductor element is detected, generating at least one control signal configured to apply the deduced gate voltage Vcc or VEE to the module (Fig. 4, when you have a negative VD and VS positive VG will apply deduced gate voltage).
Claim 9, Spessot discloses (Figs. 1-4) the method according to claim 1 wherein a part of the method forms an iterative loop such that the series of operations b to d are reiterated at least one time, starting from an acquisition of a second value VsoH,x+1 a second time (Fig. 3 shows the same model of Fig. 2 but adds an iterative loop, Para [0089]).
Claim 11, Spessot discloses (Figs. 1-4) the method according to claim 1 wherein criteria to deduce the delay time of the turn-on toN or the delay time of the turn-off tOFF is further dependent from the ON-state gate voltage Vcc or the OFF-state gate voltage VEE (Para [0081] states pulse duration may depend on junction implant conditions which would include Vcc and VEE) Claim 12, Spessot discloses (Figs. 1-4) a power semiconductor module comprising a single Metal- Oxide-Semiconductor element or a set of Metal-Oxide-Semiconductor elements or a single Metal-Insulator-Semiconductor element or a set of Metal-Insulated-Semiconductor elements, said module being arranged to implement the method according to claim 1 (the method of Spessot can be used to determine OSS degradation in the case of an NMOS and PMOS device, Para [0005]). Claim 13, Spessot discloses (Figs. 1-4) computer software comprising instructions to implement the method according to claim 1 when the computer software is executed by a processor (TCAD deck software can simulate the process of the measured devices, TCAD deck would use a computer processor, Para [0141]). Claim 14, Spessot discloses (Figs. 1-4) Computer-readable non-transient recording medium on which a software is registered to implement the method according to claim 1 when the software is executed by a processor (TCAD deck software can simulate the process of the measured devices, where TCAD can be on a recording medium and TCAD deck would use a computer processor, Para [0141]).
Allowable Subject Matter
Claim 10 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten to overcome the 112 rejection above and in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the closest prior art of record, Spessot (US 2015/0171857), fail to disclose (by themselves or in combination) the following limitations in combination with the rest of the claim:
Regarding Claim 10, - if the temporal derivative of the said acquired second values dVsoh,X/dt is positive, the ON-state gate voltage Vcc is decreased with respect to a previous value of the ON-state gate voltage Vcc the OFF-state gate voltage VEE is decreased with respect to a previous value of the OFF- state gate voltage VEE; - if the temporal derivative of the said acquired second values dVsoh,X/dt is negative, the ON-state gate voltage Vcc is increased with respect to a previous value of the ON-state gate voltage Vcc or the OFF-state gate voltage VEE is increased with respect to a previous value of the OFF- state gate voltage VEE.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUSTAVO G RAMALLO whose telephone number is (571)272-9227. The examiner can normally be reached Monday-Friday 10am - 6pm.
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/GUSTAVO G RAMALLO/Examiner, Art Unit 2812
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