DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Remarks
The 08/16/2024 amendments of claims 1-21 have been noted and entered.
Priority
The instant application claim of the priority date of 02/28/2022 of the foreign application JP 2022-030028 is noted and entered. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 08/16/2024 and 08/22/2024 were filed after the mailing date of the application on 08/16/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the first and second charge detectors described in claim 5 as: “… a first charge detector disposed around a first voltage applicator; and a second charge detector disposed around a second voltage applicator…” (emphasis added), must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 5 and all its dependent claims are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 5; claim 5 contains the limitations: “… wherein the semiconductor layer is configured between the optical member and a wiring layer, and includes: a first charge detector disposed around a first voltage applicator; and a second charge detector disposed around a second voltage applicator, and the transmission suppressor is configured in a region at least excluding the first charge detector and the second charge detector.” (emphasis added). The specification and the drawings portions of the disclosure do not contain any details or representations of these limitations.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3, 6-7, 9 and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Matsumoto, US 20200066775 A1 (Matsumoto).
Regarding claim 1; Matsumoto teaches a light receiving device (Matsumoto: Annotated Fig (8) shared in this OA: 10G) comprising
a plurality of pixels ([0109]: “… or may be an imaging element having pixels for phase difference detection”),
each of the pixels (10G) including: a multifocal optical member (13-1;13-2;13-3;11; the fact that the optical member has three different lenses means that is multifocal) having a plurality of optical axes (Optical Axes; the three lenses 13-1, 13-2 and 13-3 have different optical axes as can be seen in the Fig (8));
a semiconductor layer (11) that receives light that is in a predetermined wavelength range ([0042]: “… Thus, in a pixel which receives light, like infrared light, in a wavelength band...”) and has passed through the optical member (13-1; 13-2; 13-3; 11), to perform photoelectric conversion (10G is an avalanche photodiode (APD)); and
a transmission suppressor (31-1; 31-2;31-3) that suppresses, on a first surface (First Surface), on a side opposite to a light incident side (Light Incident Side), of the semiconductor layer (11), transmission of the light through the semiconductor layer ([0031]: “… In addition, the metal wirings 31 each have a function as a reflection film which reflects the light having passed through the semiconductor substrate 11”).
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Regarding claim 3; Matsumoto teaches all the limitations of the light receiving device according to claim 1.
Matsumoto teaches wherein each of the pixels further includes a multiplication region section (Matsumoto: Annotated Fig (8) shared in this OA: 21) that multiplies carriers generated through the photoelectric conversion ([0030]: “… The avalanche multiplication region 21 can multiply carriers (e−) generated through the photoelectric conversion of the light incident on the semiconductor substrate 11.”), and on the first surface (First Surface), the transmission suppressor (31-1; 31-2; 31-3) is configured around the multiplication region section (21).
Regarding claim 6; Matsumoto teaches all the limitations of the light receiving device according to claim 1.
Further, Matsumoto teaches wherein the semiconductor layer (Matsumoto: Annotated Fig (8) shared in this OA: 11) includes a photodiode (10G; [0067]), and the transmission suppressor (31-1; 31-2; 31-3) is configured to overlap the photodiode (10G) in plan view.
Regarding claim 7; Matsumoto teaches all the limitations of the light receiving device according to claim 1.
Further, Matsumoto teaches wherein the transmission suppressor (Matsumoto: Annotated Fig (8) shared in this OA: 31-1; 31-2; 31-3) includes an uneven structure formed on the first surface (First Surface) of the semiconductor layer (11).
Regarding claim 9; Matsumoto teaches all the limitations of the light receiving device according to claim 7.
Further, Matsumoto teaches wherein the uneven structure (Matsumoto: Annotated Fig (8) shared in this OA: structure of 31-1; 31-2, 31-3) is formed by digging a plurality of trenches (separations between the elements of 31-1; 31-2, 31-3) that becomes recessed shapes at predetermined intervals in the semiconductor layer (12).
Regarding claim 21; Matsumoto teaches an electronic apparatus (Matsumoto: [0001]) comprising the light receiving device of claim 1 (Annotated Fig (8) shared in this OA: 10G).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claims 2, 4, 8 and 10-20 are rejected under 35 U.S.C. 103 as being unpatentable over Matsumoto, US 20200066775 A1 (Matsumoto) in view of Yokogawa et al, US 20210288192 A1 (Yokogawa)
Regarding claim 2; Matsumoto teaches all the limitations of the light receiving device according to claim 1.
Further, Matsumoto teaches wherein the optical member (Matsumoto: Annotated Fig (8) shared in this OA: 13-1; 13-2; 13-3; 11) includes a plurality of on-chip lenses (13-1; 13-2; 13-3), and the optical member (13-1; 13-2; 13-3; 11) has the plurality of optical axes (the fact that the device has multiple lenses such as (13-1; 13-2; 13-3) indicates that it has a plurality of optical axis associated with the various lenses) having incident-side vertex portions (light passing through the different lenses on different optical axes makes vertex portions at the base of the lenses) of the plurality of on-chip lenses (13-1; 13-2; 13-3) as base points, and zero-order light that passes through the plurality of optical axes enters the transmission suppressor.
Matsumoto does not teach zero-order light that passes through the plurality of optical axes enters the transmission suppressor.
Yokogawa teaches zero-order light that passes through the plurality of optical axes enters the transmission suppressor (Yokogawa: Fig (1-B): 34; [0065] Then, as illustrated in B of FIG. 1, incident light that has entered the semiconductor layer 31 is diffracted by the reflection suppressing part 33, and the uneven structure of the transmission suppressing part 34 suppresses transmission through the semiconductor layer 31 of a 0th-order light component that has advanced straight through the semiconductor layer 31 of the incident light”).
Matsumoto and Yokogawa are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Matsumoto by constructing the device such that the zero-order light passes to the light transmission suppressor to suppress its transmission through the rest the circuit substrates to lower the noise production in the device and thus improve the accuracy of the device.
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Regarding claim 4; Matsumoto teaches all the limitations of the light receiving device according to claim 1
Matsumoto teaches wherein the transmission suppressor (Matsumoto: Annotated Fig (8) shared in this OA: 31-1; 31-2; 31-3) is configured in a region of the semiconductor layer (11+12) in which a photoelectric conversion device (10G) is disposed, the region excluding a range in which a transistor to be used for drive of a corresponding one of the pixels is disposed.
Matsumoto does not teach the region excluding a range in which a transistor to be used for drive of a corresponding one of the pixels is disposed.
Yokogawa teaches the region (Yokogawa: Fig (31-B): 23) excluding a range in which a transistor (71) to be used for drive of a corresponding one of the pixels (11) is disposed.
Matsumoto and Yokogawa are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Matsumoto by constructing the region to exclude a range in which a transistor to be deposited to better utilize the space on the chip by increasing the density of components on the chip leading to more processing speed and thus better performance of the device.
Regarding claim 8; Matsumoto teaches all the limitations of the light receiving device according to claim 7.
However, Matsumoto does not teach wherein a pitch of the uneven structure is 200 nm or more and 1,000 nm or less.
Yokogawa teaches wherein a pitch of the uneven structure is 200 nm or more and 1,000 nm or less (Yokogawa: [0217]: “… Furthermore, a horizontal axis indicates a pitch size of a diffractive structure formed in the transmission suppressing part 34 (that is, an uneven structure of the transmission suppressing part 34 according to each of the embodiments described above and in each of the configuration examples described above). Then, FIG. 32 illustrates a result of simulating a sensitivity with respect to a size of a pitch of the uneven structure for each wavelength (750 nm, 850 nm, or 950 nm) of incident light that enters the pixel 11”).
Matsumoto and Yokogawa are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art to modify Matsumoto by using the pitch sizes disclosed in Yokogawa to improve the sensitivity of the pixel leading to a better performing device ([0218]-[0219]).
Regarding claim 10; Matsumoto teaches all the limitations of the light receiving device according to claim 7.
Matsumoto teaches wherein the semiconductor layer (Matsumoto: Annotated Fig (8) shared in this OA: 11) includes a photoelectric conversion device (10G), and a protruding structure of the uneven structure includes a dummy gate electrode in a potential floating state or a state of being fixed at a ground potential, the dummy gate electrode being formed when a gate electrode of a transistor is formed, the transistor being used for drive of a corresponding one of the pixels including the photoelectric conversion device.
Matsumoto does not teach a protruding structure of the uneven structure includes a dummy gate electrode in a potential floating state or a state of being fixed at a ground potential, the dummy gate electrode being formed when a gate electrode of a transistor is formed, the transistor being used for drive of a corresponding one of the pixels including the photoelectric conversion device.
Yokogawa teaches a protruding structure of the uneven structure (Yokogawa: Annotated Fig (11-A) shared in this OA: structure of the suppressor structure 34D) includes a dummy gate electrode (Dummy Gate) in a potential floating state or a state of being fixed at a ground potential (Claim 5 of Yokogawa), the dummy gate electrode (Dummy Gate) being formed when a gate electrode of a transistor is formed (52a; 52,b; Claim 5 of Yokogawa), the transistor being used for drive of a corresponding one of the pixels (Claim 5 of Yokogawa) including the photoelectric conversion device (11D).
Matsumoto and Yokogawa are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Matsumoto by constructing the dummy gates as disclosed in Yokogawa to improve the suppression effect of the suppressor structure leading to a lower rate of noise production which in turn leads to a better performing device.
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Regarding claim 11; Matsumoto teaches all the limitations of the light receiving device according to claim 7.
Matsumoto does not teach wherein the transmission suppressor includes an uneven structure formed by digging, at predetermined intervals, a plurality of trenches that becomes recessed shapes in the first surface of the semiconductor layer and disposing, at predetermined intervals, a plurality of protruding structures that becomes protruding shapes on the first surface of the semiconductor layer.
Yokogawa teaches wherein the transmission suppressor (Yokogawa: Fig (1-B): 34) includes an uneven structure (see the structure of 34) formed by digging, at predetermined intervals, a plurality of trenches (trenches between 34 portions) that becomes recessed shapes in the first surface (surface on which 34 is constructed) of the semiconductor layer (21) and disposing, at predetermined intervals, a plurality of protruding structures(34) that becomes protruding shapes on the first surface (surface on which 34 is constructed) of the semiconductor layer (21).
Matsumoto and Yokogawa are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of instant application, to a person having ordinary skill in the art, to modify Matsumoto by constructing the uneven structure of the suppressor at the predetermined intervals disclosed in Yokogawa to create a diffraction grating able to diffract the incident light as to increase the sensitivity of the detector pixel ([0218]-[0219]) thus leading to a better performing device.
Regarding claim 12; Matsumoto teaches all the limitations of the light receiving device according to claim 7.
Matsumoto does not teach wherein the uneven structure is formed by providing, on the first surface of the semiconductor layer, at predetermined intervals, a plurality of quadrangular pyramid shapes or inverted quadrangular pyramid shapes including slopes having an inclination angle according to a plane index of a crystal plane of a single crystal silicon wafer that configures the semiconductor layer.
Yokogawa teaches wherein the uneven structure (Yokogawa: Fig (14) shared in this OA: 34F) is formed by providing, on the first surface of the semiconductor layer (surface on which 34F is constructed), at predetermined intervals, a plurality of quadrangular pyramid shapes or inverted quadrangular pyramid shapes including slopes having an inclination angle according to a plane index of a crystal plane of a single crystal silicon wafer that configures the semiconductor layer ([0128]: “Stated another way, the transmission suppressing part 34F includes, for example, an uneven structure formed by providing, at predetermined intervals, a plurality of quadrangular pyramid shapes or reversed quadrangular pyramid shapes that includes a slope having an inclination angle according to a plane index of a crystal surface of a single crystal silicon wafer that configures the semiconductor layer 31”).
Matsumoto and Yokogawa are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Matsumoto by constructing the uneven structure of the transmission suppressor as quadrangular pyramid shape to improve its ability to diffract the incident light leading to an increase in the sensitivity of the detection pixel ([0218]-[0219]).
Regarding claim 13; Matsumoto teaches all the limitations of the light receiving device according to claim 7.
Matsumoto does not teach wherein the uneven structure is formed of a plurality of polysilicons, and is floated or fixed at a ground potential.
Yokogawa teaches wherein the uneven structure (Yokogawa: Fig (6): 34C) is formed of a plurality of polysilicons, and is floated or fixed at a ground potential ([0090]: “… For example, a dummy electrode included in the transmission suppressing part 34C can include polysilicon similarly to the gate electrode 52, and is stacked on the circuit surface of the semiconductor layer 31 via an insulating film 51. Furthermore, this dummy electrode electrically floats, or is fixed at a ground potential.”).
Matsumoto and Yokogawa are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Matsumoto by constructing the uneven structure and electrically biasing it as disclosed in Yokogawa to improve the isolation of the signals between the different device portions leading to a device that is more reliable.
Regarding claim 14; Matsumoto teaches all the limitations of the light receiving device according to claim 1
Matsumoto teaches wherein the optical member (Matsumoto: Annotated Fig (8) shared in this OA: 13-1; 13-2; 13-3; 11) has the plurality of optical axes (given the multitude of the lenses this implies that the optical layer containing them has a plurality of optical axes), zero-order light that passes through the plurality of optical axes enters the transmission suppressor, and the plurality of optical axes is symmetric with respect to a predetermined point of the first surface (optical axes of the various lenses 13-1 to 13-3 can be seen to be symmetric around a point in the center of the first surface of the device).
However, Matsumoto does not teach zero-order light that passes through the plurality of optical axes enters the transmission suppressor.
Yokogawa teaches zero-order light that passes through the plurality of optical axes (Yokogawa: Annotated Fig (1-B) shared in this OA: 0th order light ray shown on the optical axis) enters the transmission suppressor (34).
Matsumoto and Yokogawa are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Matsumoto by constructing the device such that the zero-order light passing through the optical axes enters the transmission suppressor to reduce the light transmitted through the circuit layers of the device and thus reduce the noise in the device leading to a more reliable and better performing device.
Regarding claim 15; Matsumoto in view of Yokogawa teaches all the limitations of the light receiving device according to claim 14.
Matsumoto teaches wherein the plurality of optical axes (Matsumoto: Annotated Fig (8) shared in this OA: Optical Axes) is point-symmetric with respect to the predetermined point (Predetermined Symmetry Point).
Regarding claim 16; Matsumoto in view of Yokogawa teaches all the limitations of the light receiving device according to claim 14.
Matsumoto teaches wherein each of the pixels (Matsumoto: Annotated Fig (8) shared in this OA: 10G) further includes a multiplication region (21) section that multiplies carriers generated through the photoelectric conversion ([0030]: “… The avalanche multiplication region 21 can multiply carriers (e−) generated through the photoelectric conversion of the light incident on the semiconductor substrate 11.”), and the predetermined point (Predetermined Symmetry Point) includes a point configured within a light incident-side surface of the multiplication region section (21).
Regarding claim 17; Matsumoto teaches all the limitations of the light receiving device according to claim 1.
Matsumoto teaches wherein the optical member (Matsumoto: Annotated Fig (8) shared in this OA: 13-1; 13-2; 13-3; 11) includes any one of two on-chip lenses (13-1; 13-2), four on-chip lenses, eight on-chip lenses, and nine on-chip lenses, and zero-order light that passes through the plurality of optical axes having incident-side vertex portions of the plurality of on-chip lenses as base points enters the transmission suppressor.
Matsumoto does not teach and zero-order light that passes through the plurality of optical axes having incident-side vertex portions of the plurality of on-chip lenses as base points enters the transmission suppressor.
Yokogawa teaches and zero-order light (Yokogawa: Annotated Fig (1-B) shared in this OA: 0th order light passing through the optical axis of the lens) that passes through the plurality of optical axes having incident-side vertex portions of the plurality of on-chip lenses (41) as base points enters the transmission suppressor (34).
Matsumoto and Yokogawa are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Matsumoto by constructing the on-chip lenses such that the zero-order light that passes through the optical axis enters the transmission suppressor to reduce the noise levels in the device leading to a better performing device.
Regarding claim 18; Matsumoto in view of Yokogawa teaches all the limitations of the light receiving device according to claim 17.
Matsumoto teaches wherein the optical member (Matsumoto: Fig (4): 13-1; 13-2; 13-3; 41; 42; 11) includes a lens (13-1; 13-2; 13-3; 42), and the optical member includes a transparent material (41; [0056]: “…In addition, in the inner lens layer 41, for example, one inner lens 42 is formed for one pixel region of the APD sensor 10C within a transparent resin layer, and the inner lens 42 further condenses the light condensed by the plurality of on-chip lenses 13 on the center of the one pixel region”).
While Fig (4) discloses a different embodiment of the invention than what has been disclosed above in Fig (8), the two embodiments are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify the first embodiment disclosed in Fig (8) of Matsumoto by adding the transparent material disclosed in the second embodiment detailed in Fig (4) of Matsumoto to improve the protection of the device against environmental factors and to enhance the collection of light incident on the detector leading to a more reliable and better performing device.
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Regarding claim 19; Matsumoto teaches all the limitations of the light receiving device according to claim 17.
Matsumoto teaches wherein the optical member (Matsumoto: Annotated Fig (8) shared in this OA: 13-1; 13-2; 13-3; 11) includes a lens (13-1; 13-2; 13-3), and the optical member (13-1; 13-2; 13-3; 11) includes an inorganic substance ([0029]: “… It should be noted that as the semiconductor substrate 11, in addition to silicon, a material suitable for detection of infrared light may be used. For example, a compound semiconductor such as GaAs (Gallium Arsenide), InGaAs (Indium Gallium Arsenide), or CIGS (Cu, In, Ga, Se) may also be used”).
Regarding claim 20; Matsumoto teaches all the limitations of the light receiving device according to claim 1.
Matsumoto does not teach wherein each of the pixels further includes a reflection suppressor that suppresses reflection of the light on a light incident-side surface of the semiconductor layer.
Yokogawa teaches wherein each of the pixels (Yokogawa: Annotated Fig (1-B) shared in this OA: 11) further includes a reflection suppressor (33) that suppresses reflection of the light on a light incident-side surface (light Incident Side) of the semiconductor layer (31;[0058] Furthermore, in the pixel 11, a reflection suppressing part 33 that suppresses reflection of light that enters the semiconductor layer 31 is formed on the light receiving surface of the semiconductor layer 31.”).
Matsumoto and Yokogawa are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Matsumoto by constructing the reflection suppressor as disclosed in Yokogawa to lower the amount of light reflected away from the detection device thus increasing the sensitivity of the device and improving its performance.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Matsumoto, US 20200066775 A1 (Matsumoto) in view of Ito et al, WO 2020189103 A1 (Ito).
Regarding claim 5; Matsumoto teaches all the limitations of the light receiving device according to claim 1.
Further, Matsumoto teaches wherein the semiconductor layer (Matsumoto: Annotated Fig (8) shared in this OA: 11) is configured between the optical member (13-1; 13-2; 13-3; 11) and a wiring layer (12), and includes: a first charge detector disposed around a first voltage applicator; and a second charge detector disposed around a second voltage applicator, and the transmission suppressor (31-1; 31-2; 31-3) is configured in a region at least excluding the first charge detector and the second charge detector.
Matsumoto does not teach a first charge detector disposed around a first voltage applicator; and a second charge detector disposed around a second voltage applicator.
Ito teaches a first charge detector (Ito: Fig (11A): 12; Page: 5 Lines: 26-28 of the translated copy of Ito attached to this OA: “The pinning layer 12 accumulates holes. An anode 13 is connected to the pinning layer 12, and bias adjustment is possible from the anode 13.”) disposed around a first voltage applicator (13); and a second charge detector (12) disposed around a second voltage applicator (13).
Matsumoto and Ito are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Matsumoto by constructing the first and second charge detectors as disclosed in Ito to improve the ability of the device to convert the light signal into a detectable electrical signal leading to a more reliable device.
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Conclusion
Prior art made of record but not relied upon is considered pertinent to applicant’s disclosure:
Ootsuka et al, WO-2015122300-A1 (Ootsuka); discloses a multifocal lens system, a photodiode for photoelectric conversion and transistors for driving the detector system.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Moataz Khalifa whose telephone number is (703)756-1770. The examiner can normally be reached Monday - Friday (8:30 am - 5:00).
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/M.K./Examiner, Art Unit 2817
/ANTONIO B CRITE/Primary Examiner, Art Unit 2817
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