Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 2/18/26 and 11/7/24 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to because the different block in Figures 1-16 are labeled with reference numerals, it is suggested (required) that reference characters accompany the reference numerals to better understand and quickly identify the different blocks of the drawings. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-2, 4, 6, 12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over
Lin (US 2006/0176200) in view of Cho (US 2007/0126616).
A time-interleaved current-steering digital to analog converter, TI-IDAC comprising: a first sub-DAC , a second sub-DAC (14R-14G-14B Fig. 1A), a load switch and an interleaving switch arranged between the sub-DACs and the load switch (16R-16G-16B Fig. 1A) wherein the interleaving switch is being configured to interleave between the sub-DACs (SWR3-SWG3-SWB3 Fig. 1A) ((it is to be noted that these switches are interleaving switches since the they are turning on and off in alternating order)) by control (50 Fig. 1A) of a connection between the first sub-DAC and an input port of the load switch, and control (50 Fig. 1A) of a connection between the second sub-DAC and the input port of the load switch.
Lin fails to disclose:
the load switch is being configured such that the input port of the load switch is connected to a reset load of the TI-IDAC at least when the interleaving switch changes at least one of the connections between the sub-DACs and the input port of the load switch.
Cho discloses:
In Fig. 5, a first digital to analog converter and a second digital to analog converter whose outputs are couple a first and a second decoder: the output of the decoder 22 randomly reset by the first random selection switch 24, and a second current switch driver 27 for driving a current switch of the second current source previously selected by receiving the output of the delay synchronization buffer 23 randomly reset by the second random selection switch 25 (para 44).Therefore, it would have been obvious to one having ordinary skill in the art presented with the teaching of Cho before the effective filing date of the application to modify the DAC device of Lin by adding a reset load to the output of the converter for the benefit to effectively synchronize the output of the interleaved converter.
With regard to claim 2, Lin discloses:
The time-interleaved current-steering digital to analog converter of claim 1, wherein the load switch is configured to connect the input port of the load switch to either the reset load (170) or an output load (150) (Fig. 1).
(Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin and Cho as applied to claim 1 above, and further in view of Tsang (US 2008/0198053).
Lin and Cho fail to disclose:
The time-interleaved current-steering digital to analog converter claim 1, wherein a first data signal is provided to the first sub-DAC controlled by a first data latching clock signal and a second data signal is provided to the second sub-DAC controlled by a second data latching clock signal being an inverse of the first data latching clock signal.
Tsang discloses:
The active-idle cycles of sub-DAC 11 and sub-DAC 12 are orthogonal (or opposite) to each other (Fig. 1; para 21). Therefore, it would have been obvious to one having ordinary skill before the effective filing date of the application to use the teaching of Tsang in the device of Lin and Cho for the benefit to alternately process the digital to analog converters at a predetermined interval.
With regard to claim 6, Lin and Cho fail to teach:
6. The time-interleaved current-steering digital to analog converter of claim 1, wherein the interleaving switch is configured, by the interleaving clock signals, to connect each of the sub- DACs to either the input port of the load switch or to an interleaving load. Anyone having ordinary skill in the art would have known that a clock system is necessary to set the interval, the timing of the interleaving switch.
With regard to claim 12, Lin discloses:
12.The time-interleaved current-steering digital to analog converter of claim 1, further comprising a third sub-DAC and wherein the interleaving switch is further configured to interleave between the sub-DACs by control of a connection between the third sub-DAC and an input port of the load switch by a third interleaving signal (Fig. 1A).
With regard to claim 13, Lin discloses:
13. (Currently Amended) The time-interleaved current-steering digital to analog converter of claim 1, wherein each of the sub-DACs comprises one or more DAC cells. Each DAC represents one DAC cell.
7. (Claim(s) 14-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin and Cho as applied to claim 1 above, and further in view of Fontaine et al. (US 2005/0258992).
With regard to claim 14 Lin and Cho fail to disclose:
14. The time-interleaved current-steering digital to analog converter of claim 1, wherein the TI-IDAC is comprised in an integrated circuit, IC.
Fontaine discloses:
A time interleaved digital to analog converter that is mounted on an integrated circuit. Anyone having working knowledge in the art presented with the teaching of Fontaine would have been motivated before the effective filing date of the invention to integrate the DAC of Lin and Cho in an integrated circuit for the benefit to provide a compact electronic circuit so critical in communication system.
With regard to claim 15, Lin and Cho fail to disclose:
15.The time-interleaved current-steering digital to analog converter of claim 1, wherein the TI-IDAC is comprised in an electronic equipment.
Fontaine discloses:
The Time interleaved digital to analog converter is suitable for wireless (para 6). communications. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the application to use the teaching of Fontaine in the DAC converter of Lin and Cho to improve performance and reliability of the converter.
With regard to claim 16 Lin and Cho fail to disclose:
16.The electronic equipment time-interleaved current- steering digital to analog converter of claim 15, wherein the electronic equipment is a network node.
Fontaine disclose an integrated circuit. It is to be noted that discloses an integrated circuit. It is well known in the art that integrated circuit comprises a plurality of nodes connected to different parts of the circuit. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the application to use the teaching of Fontaine in the DAC converter of Lin and Cho to improve performance and reliability of the converter.
With regard to claim 17 Lin, Cho and Fontaine fail to disclose:
17. The electronic equipment time-interleaved current- steering digital to analog converter of claim 16, wherein the network node is a base station, BS, of a wireless communications network.
It is known in the art the art that a base station is necessary in communication system for it serves as a main communication point for wireless device so critical for data and internet connectivity.
With regard to claim 18 Lin and Cho fail to disclose:
18. The electronic equipment time-interleaved current- steering digital to analog converter of claim 15, wherein the electronic equipment is a wireless device.
Fontaine discloses:
The Time interleaved digital to analog converter is suitable for wireless (para 6). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the application to use the teaching of Fontaine in the DAC converter of Lin and Cho to improve performance and reliability of the converter.
With regard to claim 19 Lin and Cho fail to disclose:
19. The electronic equipment time-interleaved current- steering digital to analog converter of claim 18, wherein the wireless device is a user equipment, UE, of a wireless communications network.
Fontaine discloses
The Time interleaved digital to analog converter is suitable for wireless (para 6).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the application to use the teaching of Fontaine in the DAC converter of Lin and Cho to improve performance and reliability of the converter.
Allowable Subject Matter
Claims 3, 5, 7-11 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 20-25 and 27 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: the above prior art fails to teach the limitations of: controlling a load switch to connect the input port of the load switch to the reset load; subsequently controlling the interleaving switch to connect the first sub-DAC to the input port of the load switch and to disconnect the second sub-DAC from the input port of the load switch and subsequently controlling the load switch to connect the input port of the load switch to the output load.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PEGUY JEAN PIERRE whose telephone number is (571) 272-1803. The examiner can normally be reached from 8:00-6:30 PM Monday-Thursday. The examiner’s fax phone number is (571) 273-1803. The Examiner email address is peguy.jeanpierre@uspto.gov. If attempts to reach the Examiner are unsuccessful, the Examiner’s supervisor Dameon E. Levi can be reached at (571) 272-2105.
/PEGUY JEAN PIERRE/Primary Examiner, Art Unit 2845