DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to because in Figs. 1, 12, and 13 the drawings are not specific enough to make clear what is being represented. As there is enough room within the figures it is suggested that labels are added within each of the components to describe what is being shown. For example, in the box representing the element, 3, the label “First element unit” can be placed within the box. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
Page 4, line 10 “Accordingly, according” should be “according”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 7, the claim states that it is a method of manufacturing the solid-state imaging element of claim 1. However, it fails to discuss the method of manufacturing several of the elements included within claim 1. It does not discuss the process of forming of either the first element and the second element within claim 1, which are pivotal elements that are connected to the claimed transfer part and capacitance part. This leaves it unclear to whether or not the listed steps actually manufacture the full imaging element claimed in claim 1. Claims 8-10 are also rejected for the same reason as they are dependent on claim 7 and do not overcome the described ambiguity.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3 and 6-10 are rejected under 35 U.S.C. 103 as being unpatentable over Watanabe et al. (JP 2004063627 A) in view of Kobayashi (JP 06334164 A).
Regarding claim 1, Watanabe et al. teaches A solid-state imaging element comprising:
a semiconductor substrate (Figure 1E shows a substrate, 1);
a first element unit formed on the semiconductor substrate (Fig 1E shows a first element unit, L); and
a second element unit formed on the semiconductor substrate (Fig 1E shows a second element unit, R), wherein
the first element unit includes a light receiving part configured to generate charges in response to incidence of light (Paragraph 0008 describes L as a light receiving portion), and a transfer part configured to transfer the charges (Paragraph 0037 describes the transfer gate formation area, 7, being in the first element unit, L),
the second element unit is configured to perform at least one of transmission of a signal to the first element unit and reception of a signal from the first element unit (It is known within the art that peripheral circuits both transmit and receive signals), and includes at least one capacitance part (Paragraph 0037 describes the capacitor formation area, 10, in the second element unit, R),
the transfer part includes
a first transfer electrode and a second transfer electrode that are aligned in a transfer direction of the charges (Fig 1E shows two transfer electrodes, 8 and 24, aligned in a transfer direction), and
a first insulating layer configured to insulate the first transfer electrode and the second transfer electrode from each other (Paragraph 0037 describes the first insulating film, 9, being formed on top of the first transfer electrode, 8. Fig 1D shows the insulating film, 9, directly formed on the top surface of the first transfer electrode, 11. Fig 1E shows the second transfer electrode, 24, is formed above the insulating film, 9, labeled in Fig 1D),
the at least one capacitance part includes
a first capacitance electrode and a second capacitance electrode that overlap each other as viewed from a thickness direction of the semiconductor substrate (Fig 1E shows a first capacitance electrode, 11, and a second capacitance electrode, 25, overlapping each other from the thickness direction), and
a second insulating layer configured to insulate the first capacitance electrode and the second capacitance electrode from each other (Paragraph 0037 describes the second insulating film, 12, being formed on top of the capacitance electrode, 11. Fig 1D shows the insulating film, 12, directly formed on the top surface of the first capacitance electrode, 11. Fig 1E shows the second capacitance electrode, 25, is formed above the insulating film, 11, labeled in Fig 1D),
as viewed from the thickness direction of the semiconductor substrate, a part of the first transfer electrode overlaps a part of the second transfer electrode (Fig 1E shows that the first transfer electrode, 9, overlaps with the second transfer electrode, 24),
the first insulating layer includes a first portion positioned between the part of the first transfer electrode and the part of the second transfer electrode (Fig 1D shows the insulating film, 9, directly formed on the top surface of the first transfer electrode, 11. Fig 1E shows the second transfer electrode, 24, is formed above the insulating film, 9, labeled in Fig 1D. Thus, the first insulating layer is between the two transfer electrodes),
the second insulating layer includes a second portion positioned between the first capacitance electrode and the second capacitance electrode (Fig 1D shows the insulating film, 12, directly formed on the top surface of the first capacitance electrode, 11. Fig 1E shows the second capacitance electrode, 25, is formed above the insulating film, 11, labeled in Fig 1D. Thus, the second insulating layer is between the two capacitance electrodes), and
Watanabe et al. does not teach a thickness of the first portion of the first insulating layer is larger than a thickness of the second portion of the second insulating layer.
Kobayashi teaches a thickness of the first portion of the first insulating layer is larger than a thickness of the second portion of the second insulating layer (Paragraph 11 describes the thickness of the first insulating layer, 26B, having a larger thickness than the second insulating film, 26A. Figure 5 also shows that the thickness, d3, of 26B, is larger than the thickness, d2, of 26A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Watanabe et al to have the first insulating layer be thicker than the second insulating layer, as taught in Kobayashi, because it allows to tailor capacitance to the specific insulating layer as capacitance is inversely proportional to dielectric thickness. Allowing one insulating layer to be thicker allows for reduced capacitance which improves temporal resolution.
Regarding claim 2, Watanabe et al., as modified, does teach that the first insulating layer is formed integrally with the second insulating layer.
Kobayashi teaches that the first and second insulating layer are integrally formed (Fig 4 shows that the two insulating layers, 26A and 26B, are integrally connected to each other).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Watanabe et al to make the first and second insulating layer integrally formed, as taught in Kobayashi, because integrally formed layers reduces the number of assembly steps which improve mechanical stability and reduces the chances of defects.
Regarding claim 3, Watanabe et al., as modified, teaches the thickness of the first portion of the first insulating layer is twice or more the thickness of the second portion of the second insulating layer (Fig 4 of Kobayashi shows that the first thicknesses taught in for claim 1, d3, is at least twice the thickness of the second thickness taught in, d2).
Regarding claim 6, Watanabe et al., as modified, teaches an operating voltage of the first element unit is higher than an operating voltage of the second element unit (Paragraphs 0007-0010 describe that the thickness is directly correlated to the amplitude of the inside the element, which is the maximum possible operating voltage. An increase in the thickness of the insulating layer results in an increase in the amplitude. Therefore, with the modifications made to Watanabe with Kobayashi in claim 1, the first element would have a larger operating voltage than the second element as the first insulating layer in the first element is thicker than the second insulating layer in the second element)
Regarding claim 7, Watanabe et al., as modified, teaches a method for manufacturing the solid-state imaging element according to claim 1, the method comprising:
a step of preparing the semiconductor substrate (Fig 1A shows a substrate, 1);
a step of forming the first transfer electrode and the first capacitance electrode on the semiconductor substrate (Fig 1B shows a first transfer electrode, 8, and a first capacitance electrode, 11 being formed on the substrate, 1);
a step of forming the first insulating layer on at least the first transfer electrode and forming the second insulating layer on at least the first capacitance electrode (Fig 1B shows a first insulating layer, 9, and a second insulating layer, 12, formed on the first transfer electrode, 8, and the first capacitance electrode, 11, respectively);
a step of adjusting a thickness of at least one of a portion of the first insulating layer positioned on the first transfer electrode and a portion of the second insulating layer positioned on the first capacitance electrode (Paragraph 0037 describes the first insulating layer, 9, being formed from multiple layers stacked onto each other therefore increasing the thickness from the initial insulating layer)
a step of forming the second transfer electrode and the second capacitance electrode on the semiconductor substrate (Fig 1E shows the second transfer electrode, 24, and the second capacitance electrode, 25, formed on the semiconductor substrate, 1)
Watanabe et al., as modified, does not teach a step of adjusting a thickness of at least one of a portion of the first insulating layer positioned on the first transfer electrode and a portion of the second insulating layer positioned on the first capacitance electrode such that the thickness of the portion of the first insulating layer is larger than the thickness of the portion of the second insulating layer.
Kobayashi teaches that the thickness of the portion of the first insulating layer is larger than the thickness of the portion of the second insulating layer (Paragraph 11 describes the thickness of the first insulating layer, 26B, which is between two transfer electrodes, being larger than that of the second insulating layer, 26A)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Watanabe et al to have the step of changing the thickness of the insulating layer be used for the purpose of making the thickness of the first insulating layer larger than the second insulating layer, as taught in Kobayashi, because it allows to tailor capacitance to the specific insulating layer as capacitance is inversely proportional to dielectric thickness. Allowing one insulating layer to be thicker allows for reduced capacitance which improves temporal resolution.
Regarding claim 8, Watanabe et al., as modified, teaches the step of forming the first insulating layer and forming the second insulating layer, the first insulating layer and the second insulating layer are simultaneously formed (Fig 1A and 1B show that the steps of forming the first insulating layer, 9, and the second insulating layer, 12, are formed at the same time).
Watanabe et al., as modified, does not teach that the first and second insulating layer are integrally formed.
Kobayashi teaches that the first and second insulating layer are integrally formed (Fig 4 shows that the two insulating layers, 26A and 26B, are integrally connected to each other).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Watanabe et al to make the first and second insulating layer integrally formed, as taught in Kobayashi, because integrally formed layers reduces the number of assembly steps which improve mechanical stability and reduces the chances of defects.
Regarding claim 9, Watanabe et al., as modified, does not explicitly teach the step of adjusting the thickness of the at least one of the portion of the first insulating layer and the portion of the second insulating layer, the thickness of the portion of the second insulating layer is reduced by performing an etching process on the second insulating layer.
Koboyashi discloses that one of the two insulating layers is etched in order to reduce its thickness (Paragraph 25 describes an insulating layer, 26B, being selectively etched).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Watanabe et al. to use that same etching process to the reduce the thickness of the second insulating layer, as taught in Koboyashi, because the process of etching allows for more precise control over the fabrication process while reducing processing time and avoiding extra deposition steps.
Regarding claim 10, Watanabe et al. teaches the step of adjusting the thickness of the at least one of the portion of the first insulating layer and the portion of the second insulating layer, the thickness of the portion of the first insulating layer is increased by performing a film forming process on the first insulating layer (Paragraph 0037 describes the first insulating layer, 9, being formed from multiple layers stacked onto each other).
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Watanabe et al. (JP 2004063627 A) in view of Kobayashi (JP 06334164 A) as applied to claim 1 above, and further in view of Muramatsu et al. (WO2021/049140, using the English document US 20220208809 A1 as the translations, all citations below are directed to US 20220208809 A1).
Regarding claim 4, Watanabe et al., as modified, teaches the second element unit including a conversion part configured to convert the analog signal into digital signal (Fig 1c shows a Photoelectric conversion element formation pattern, 16, in the second element, R).
Watanabe et al., as modified, does not teach the first element unit including an amplifier part configured to convert the charge transferred by the transfer part into an analog signal.
Muramatsu et al. teaches the first element unit including an amplifier part configured to convert the charge transferred by the transfer part into an analog signal (Paragraph 0010 includes an amplifier in a first element which contains a light receiving portion).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Watanabe et al to add an amplifier to the first element unit, as taught in Muramtsu et al., because an amplifier converts the charge into measurable voltage, which is allows for the creation of more accurate low-noise images.
Regarding claim 5, Watanabe et al., as modified, does not teach the second element unit including a generation part configured to generate a drive signal for driving the first element unit.
Muramatsu et al. teaches the second element unit including a generation part configured to generate a drive signal for driving the first element unit (Paragraph 0023 describes the second element including a drive unit which generates a drive signal.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Watanabe et al to add a generation part to the second element unit, as taught in Muramtsu et al., because adding an element that generates drive signals improves signal integrity, allowing for more controlled signal outputs.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Moriwaki et al. (US 20210288099 A1) contains similar element as it is an imaging element with a light receiving element with a conversion layer, a light receiving element and several electrodes overlapping each other in the light receiving element.
(JP 2009117418 A) has an element with a light receiving unit which contains two transfer electrodes with an insulating layer sandwiched in between them.
Yasuaki (JP 2017139281 A) contains very similar elements as it contains two element units one which contains two transfer electrodes with an insulating layer in between them, the other containing two capacitance electrodes with an insulating layer in between them.
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/C.E.H./Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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