DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) was submitted on 11/7/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Preliminary Amendment
Applicant’s 8/20/2024 preliminary amendment to amend the Claims is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3 and 11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
A broad range or limitation together with a narrow range or limitation that falls within the broad range or limitation (in the same claim) may be considered indefinite if the resulting claim does not clearly set forth the metes and bounds of the patent protection desired. See MPEP § 2173.05(c). In the present instance, Claim 3 recites the broad recitation “wherein the electrical signal is a voltage signal or a current signal” in lines 2-3, and the claim also recites “in particular an increasing or decreasing voltage signal, or an increasing or decreasing current signal” in lines 3-4, which is the narrower statement of the limitation. Additionally, Claim 11 recites the broad recitations wherein the active layer includes “one or more of an oxide”, “a nitride”, or “a solid-state electrolyte” in lines 2-5, and the claim also recites “in particular one or more of a silicon dioxide, tantalum oxide, tungsten oxide, hafnium oxide and titanium oxide”, “in particular one ore more of a titanium nitride, aluminum nitride, tantalum nitride, and gallium aluminum nitride”, and “in particular a polymer” in lines 2-5, respectively, which are the narrower statements of the limitations. The claim(s) are considered indefinite because there is a question or doubt as to whether the feature introduced by such narrower language is (a) merely exemplary of the remainder of the claim, and therefore not required, or (b) a required feature of the claims. For the purposes of examination, for Claims 3 and 11 the respective narrower statements of the limitations will be considered against the prior art.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-2, and 6-15 are rejected under 35 U.S.C. 103 as being unpatentable over Galambos et al (US 12,063,461 B1, hereafter Galambos) in view of Huang et al (US 2022/0036170 A1, hereafter Huang).
Re Claim 1, Galambos discloses an integrated circuit (“single integrated circuit”; column 4, lines 26-27) comprising a resistive switching section (“memristor” in “memristor-based memory”; column 4, lines 10-11).
Galambos does not explicitly disclose a resistive switching section (“memristor” in “memristor-based memory”) with an active layer arranged between a first electrode and a second electrode, wherein the resistive switching section is configured:
to provide an electrical resistance between the first and second electrode which is switchable between different resistance values depending on an electrical signal applied to the first and the second electrode, and
to emit photons during or associated with switching between the resistance values.
However, Huang discloses a resistive switching section (FIG. 2, particularly elements 501, 401, 301, 201, which are supported by 101, 102, 103; [0038]-[0046]) with an active layer (401; [0038]) arranged between a first electrode (501; [0038]) and a second electrode (201; [0038]), wherein the resistive switching section is configured:
to provide an electrical resistance between the first and second electrode (501, 201, respectively; [0047]-[0048]) which is switchable between different resistance values depending on an electrical signal (“electrical pulses”; [0047]-[0048]) applied to the first and the second electrode (501, 201, respectively; [0047]-[0048]), and
to emit photons during or associated with switching between the resistance values ([0047]-[0048], via quantum dots).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the integrated circuit taught by Galambos with the limitations taught by Huang to use an optoelectronic synaptic memristor for the memristor-based memory to save on power consumption as taught by Huang ([0005]).
Re Claim 2, Galambos and Huang teach the integrated circuit according to Claim 1, while Huang further teaches wherein the electrical resistance is switchable between a low resistance value and a high resistance value ([0047]-[0048]).
No further modification made, see Claim 1 for obviousness statement.
Re Claim 6, Galambos and Huang teach the integrated circuit according to Claim 1, while Huang further teaches wherein for enhancing photon emission one or more of an antenna, a reflection layer (101; [0038], the initial emission of light into the device has its function “enhanced” by nature of being directed inwardly by the reflecting waveguide), and a lens is arranged.
No further modification made, see Claim 1 for obviousness statement.
Re Claim 7, Galambos and Huang teach the integrated circuit according to Claim 1, while Huang further teaches the integrated circuit comprises one or more waveguides (101; [0038]), at least some of which coupled with the resistive switching section, for enabling photon transmission ([0038]).
No further modification made, see Claim 1 for obviousness statement.
Re Claim 8, Galambos and Huang teach the integrated circuit according to Claim 1, while Galambos further teaches wherein the integrated circuit comprises a plurality of resistive switching sections (“memristor” in “memristor-based memory”; column 3, line 64 to column 4, line 11, by nature of storing a maze pattern that would require more than a single bit).
Re Claim 9, Galambos and Huang teach the integrated circuit according to Claim 1, while Galambos further teaches the integrated circuit comprises one or more electrical sections (410; column 16, lines 1-2).
Re Claim 10, Galambos and Huang teach the integrated circuit according to Claim 1, while Galambos further teaches wherein the integrated circuit is fabricated according to a CMOS process (column 7, lines 23-26, at least in part).
Re Claim 11, Galambos and Huang teach the integrated circuit according to Claim 1, while Huang further teaches wherein the active layer (401) includes one or more of an oxide, in particular one or more of a silicon dioxide ([0038]), tantalum oxide, tungsten oxide, hafnium oxide and titanium oxide, a nitride, in particular one or more of a titanium nitride, aluminum nitride, tantalum nitride, and gallium aluminum nitride, an aluminum, and a solid-state electrolyte, in particular a polymer, or one or more stacks thereof.
No further modification made, see Claim 1 for obviousness statement.
Re Claim 12, Galambos and Huang teach the integrated circuit according to Claim 1, while Huang further teaches wherein the resistive switching section (FIG. 2) includes one or more of a silver-doped hafnium dioxide, copper, hafnium dioxide, silver, titanium dioxide ([0016]), copper sulfide, amorphous silicon, silver telluride, titanium nitride, wolfram, tungsten, platinum, gold, titanium, cobalt, and/or indium tin oxide, or one or more combinations thereof.
No further modification made, see Claim 1 for obviousness statement.
Re Claim 13, Galambos and Huang teach the integrated circuit according to Claim 1, while Huang further teaches the integrated circuit includes a substrate (102; [0038]), in particular for supporting the resistive switching section ([0038], at least supporting function of).
No further modification made, see Claim 1 for obviousness statement.
Re Claim 14, Galambos and Huang teach the integrated circuit according to Claim 1, while Huang further teaches wherein the resistive switching section (FIG. 2) has an in-plane or horizontal configuration, or a vertical configuration ([0038]).
No further modification made, see Claim 1 for obviousness statement.
Re Claim 15, Galambos discloses a method for fabricating an integrated circuit (“single integrated circuit”; column 4, lines 26-27) comprising arranging a resistive switching section (“memristor” in “memristor-based memory”; column 4, lines 10-11) at the integrated circuit (“single integrated circuit”; column 4, lines 10-27).
Galambos does not explicitly disclose:
arranging at the integrated circuit (“single integrated circuit”) a first electrode and a second electrode, and
arranging an active layer between the first electrode and the second electrode, for providing a resistive switching section (“memristor” in “memristor-based memory”) which is configured:
to provide an electrical resistance between the first and second electrode which is switchable between different resistance values depending on an electrical signal applied to the first and the second electrode, and
to emit photons during or associated with switching between the resistance values.
However, Huang teaches a method (FIG. 2; [0038]-[0046]) comprising arranging at the integrated circuit (by nature of being the “memristor” in the “memristor-based memory” of Galambos) a first electrode (501; [0038]) and a second electrode (201; [0038]), and
arranging an active layer (401; [0038]) between the first electrode (501) and the second electrode (201; [0038]), for providing a resistive switching section (FIG. 2, particularly 301, 401; [0038]) which is configured:
to provide an electrical resistance between the first and second electrode (501, 201, respectively; [0047]-[0048]) which is switchable between different resistance values depending on an electrical signal (“electrical pulses”; [0047]-[0048]) applied to the first and the second electrode (501, 201, respectively; [0047]-[0048]), and
to emit photons during or associated with switching between the resistance values ([0047]-[0048], via quantum dots).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the integrated circuit taught by Galambos with the limitations taught by Huang to use an optoelectronic synaptic memristor for the memristor-based memory to save on power consumption as taught by Huang ([0005]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Galambos and Huang, as applied to Claim 1, in view of Katoh (US 2009/0046496 A1).
Re Claim 3, Galambos and Huang teach the integrated circuit according to Claim 1, while Huang further teaches wherein the electrical signal is an increasing or decreasing electrical signal ([0048], by nature an electrical pulse will be repeatedly increasing or decreasing in strength, claim language does not require a strict increase/decrease).
Galambos and Huang do not explicitly disclose wherein the electrical signal is a voltage signal or a current signal.
However, Katoh teaches a resistive switching section ([0007]-[0022]) wherein the electrical signal is a voltage signal (“voltage pulse”; [0022]) or a current signal.
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the integrated circuit of Galambos as discussed with regard to Claim 1 above with the limitations taught by Katoh to use a voltage pulse for the electrical signal as a functionally equivalent means of electrically stimulating a variable resistance element for predictable resistance changes as taught by Katoh ([0014]).
Re Claim 4, Galambos and Huang teach the integrated circuit according to Claim 1, but they do not explicitly disclose wherein the electrical resistance is switchable from a high resistance value to a low resistance value when the electrical signal crosses a first threshold, and from a low resistance value to a high resistance value when the electrical signal crosses a second threshold which is different from the first threshold.
However, Katoh teaches a resistive switching section (FIGS. 9a-9b; [0007]-[0008]) wherein the electrical resistance is switchable from a high resistance value to a low resistance value when the electrical signal crosses a first threshold (“erase voltage amplitude”; [0008]), and from a low resistance value to a high resistance value when the electrical signal crosses a second threshold (“write voltage amplitude”; [0007], particularly with multi-value resistance) which is different from the first threshold (“erase voltage amplitude”; [0007]-[0008], by nature of having multiple write voltage amplitudes).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the integrated circuit of Galambos as discussed with regard to Claim 1 above with the limitations taught by Katoh to use a plurality of voltage amplitudes for the write pulse to allow for variable resistance levels as taught by Katoh ([0007]).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Galambos and Huang, as applied to Claim 1, in view of Zheng et al (US 2018/0348128 A1, hereafter Zheng).
Re Claim 5, Galambos and Huang teach the integrated circuit according to Claim 1, but they do not explicitly disclose wherein for enhancing photon emission the resistive switching section exhibits a Purcell effect.
However, Zheng teaches ([0214]) wherein the Purcell effect is used to enhance photon emission of quantum dots (which are contained in the resistive switching section of Huang; [0214]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the integrated circuit of Galambos as discussed with regard to Claim 1 above with the limitations taught by Zheng to utilize high-quality plasmonic cavities for placement of the quantum dots to improve the spontaneous emission rate (via the Purcell effect) as taught by Zheng ([0214]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COLIN RUSSELL MCCUTCHEON whose telephone number is (703)756-1897. The examiner can normally be reached Monday-Friday, 12:30-9:30 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DREW N RICHARDS can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/COLIN RUSSELL MCCUTCHEON/Examiner, Art Unit 2892
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
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