DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
2. The information disclosure statement (IDS) submitted on August 20, 2024, has been fully considered by the examiner.
Claim Objections
3. Claims 5 and 12 are objected to because of the following informalities.
Claims 5 and 12 each recite the limitation, “the test controller generates a third selection control signal for controlling which of the one or more preset addresses to be selected for a write operation or a read operation.” To correct the grammar, Examiner suggests wording such as, “the test controller generates a third selection control signal for controlling which of the one or more preset addresses is selected for a write operation or a read operation.”
Appropriate correction is required.
Claim Interpretation
4. The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
5. The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
6. This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “computer-executable instructions for causing a computer to perform a method, the method comprising: creating, in a circuit design, a memory-testing circuit” in claim 8.
7. Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
8. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
9. Claims 1-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
10. Claim 1 recites the limitation, “perform a test on a memory in the circuit” in lines 1-2. The meaning of this limitation is indefinite.
It is unclear if “in the circuit” refers to “A memory-testing circuit” in line 1, or “a circuit configurable to perform a test,” also in line 1. It is also unclear if “configurable” describes “a memory-testing circuit” or “a circuit.”
For the purpose of this examination, Examiner shall interpret, “A memory-testing circuit in a circuit configurable to perform a test on a memory in the circuit” as “A memory-testing circuit in a circuit, the memory-testing circuit configurable to perform a test on a memory in the memory-testing circuit.” Claims 2-7 depend on claim 1.
11. Claim 1 recites the limitation "the memory” in line 2. There is insufficient antecedent basis for this limitation in the claim. For the purpose of this examination, Examiner shall interpret, “the memory” as “the memory in the memory-testing circuit.”
12. Regarding claims 1-7, Examiner believes “a memory in the circuit,” “the memory,” and “the memory to be tested” refer to the same memory. To remove ambiguity, Examiner suggests claim 1, lines 1-2, recite, “A memory-testing circuit in a circuit, the memory-testing circuit configurable to perform a test on a memory while preserving contents of the memory and comprising:” (note it is implied the memory must be “in the circuit” to be tested by the circuit, whether “in the circuit” references “a memory-testing circuit” or “a circuit”). Examiner further suggests all subsequent references in claims 1-7 be changed to “the memory” with no modifiers.
13. Claim 2 recites the limitation "the memory” in line 2. There is insufficient antecedent basis for this limitation in the claim. For the purpose of this examination, Examiner shall interpret, “the memory” as “the memory in the memory-testing circuit.”
14. Claim 3 recites the limitation "the memory” in lines 3, 5, and 6. There is insufficient antecedent basis for this limitation in the claim. For the purpose of this examination, Examiner shall interpret, “the memory” as “the memory in the memory-testing circuit.”
Claim 3 recites the limitation "the memory to be tested” in lines 2, 4, and 7. There is insufficient antecedent basis for this limitation in the claim. For the purpose of this examination, Examiner shall interpret, “the memory to be tested” as “the memory in the memory-testing circuit.”
15. Claim 7 recites the limitation "the memory” in lines 1 and 7. There is insufficient antecedent basis for this limitation in the claim. For the purpose of this examination, Examiner shall interpret, “the memory” as “the memory in the memory-testing circuit.”
16. Regarding claim 8, the claim limitation “computer-executable instructions for causing a computer to perform a method, the method comprising: creating, in a circuit design, a memory-testing circuit” invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function.
Support for this limitation is found in ¶[09] and possibly ¶[20] of the specification. These paragraphs along with the aforementioned limitation appear to teach a method that “creates” the memory-testing circuit in the circuit design (e.g., the use of schematic capture and printed circuit board layout tools, or perhaps a method that manages the manufacture of the memory-testing circuit in the circuit design). However, no description is given for how the method performs this “creation.”
Therefore, claim 8 is indefinite and rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph. Claims 9-14 depend on claim 8.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
17. Claim 8 recites the limitation "the memory” in line 4. There is insufficient antecedent basis for this limitation in the claim. For the purpose of this examination, Examiner shall interpret, “the memory” as “the memory in the circuit design.”
18. Regarding claims 8-14, Examiner believes “a memory in the circuit design,” “the memory,” and “the memory to be tested” refer to the same memory. To remove ambiguity, Examiner suggests claim 8, lines 3-4, recite, “…a memory-testing circuit configurable to perform a test on a memory while preserving contents of the memory, the memory-testing circuit comprising:” (note it is implied the memory must be “in the circuit (design)” to be tested by the circuit. Examiner further suggests all subsequent references in claims 8-14 be changed to “the memory” with no modifiers.
19. Claim 9 recites the limitation "the memory” in line 2. There is insufficient antecedent basis for this limitation in the claim. For the purpose of this examination, Examiner shall interpret, “the memory” as “the memory in the circuit design.”
20. Claim 10 recites the limitation "the memory” in lines 4, 6, and 7. There is insufficient antecedent basis for this limitation in the claim. For the purpose of this examination, Examiner shall interpret, “the memory” as “the memory in the circuit design.”
Claim 10 recites the limitation "the memory to be tested” in lines 3, 5, and 8. There is insufficient antecedent basis for this limitation in the claim. For the purpose of this examination, Examiner shall interpret, “the memory to be tested” as “the memory in the circuit design.”
21. Claim 14 recites the limitation "the memory” in lines 1 and 3. There is insufficient antecedent basis for this limitation in the claim. For the purpose of this examination, Examiner shall interpret, “the memory” as “the memory in the circuit design.”
22. Claim 15 recites the limitation "the memory” in lines 4, 6, and 7. There is insufficient antecedent basis for this limitation in the claim. For the purpose of this examination, Examiner shall interpret, “the memory” as “the memory in the circuit.”
Claim 15 recites the limitation "the memory to be tested” in lines 3, 5, and 8. There is insufficient antecedent basis for this limitation in the claim. For the purpose of this examination, Examiner shall interpret, “the memory to be tested” as “the memory in the circuit.” Claim 16 depends on claim 15.
23. Claim 16 recites the limitation "the memory” in line 2. There is insufficient antecedent basis for this limitation in the claim. For the purpose of this examination, Examiner shall interpret, “the memory” as “the memory in the circuit.”
Claim Rejections - 35 USC § 101
24. 35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
25. Claims 8-14 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claims do not fall within at least one of the four categories of patent eligible subject matter because claim 8 recites, “One or more computer-readable media storing computer-executable instructions.” Claims 9-14 depend on claim 8 and similarly recite, “The one or more computer-readable media.”
MPEP 2106.03(II) states, “the BRI of machine readable media can encompass non-statutory transitory forms of signal transmission, such as a propagating electrical or electromagnetic signal per se. See In re Nuijten, 500 F.3d 1346, 84 USPQ2d 1495 (Fed. Cir. 2007). When the BRI encompasses transitory forms of signal transmission, a rejection under 35 U.S.C. 101 as failing to claim statutory subject matter would be appropriate. Thus, a claim to a computer readable medium that can be a compact disc or a carrier wave covers a non-statutory embodiment and therefore should be rejected under 35 U.S.C. 101 as being directed to non-statutory subject matter. See, e.g., Mentor Graphics v. EVE-USA, Inc., 851 F.3d at 1294-95, 112 USPQ2d at 1134 (claims to a ‘machine-readable medium’ were non-statutory, because their scope encompassed both statutory random-access memory and non-statutory carrier waves).”
Examiner suggests claims 8-14 be amended to recite “one or more non-transitory computer-readable media” to overcome this rejection.
Claim Rejections - 35 USC § 102
26. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
27. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
28. Claims 15-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Brink, et al (US 20080209294 A1), hereinafter Brink.
Regarding independent claim 15, Brink teaches a method (FIG. 3; ¶[0006-0014]; ¶[0046-0047]) for testing a memory (FIG. 2, 220) in a circuit (FIG. 2, 200) performed by a memory-testing circuit in the circuit (FIG. 2; 210, 230, 240, 250), comprising:
reading content of one or more locations of the memory to be tested (FIG. 3, 301);
writing the content into one or more preserved locations of the memory (FIG. 3, 302);
applying a test algorithm to the one or more locations of the memory to be tested (FIG. 3, 303-307);
reading the content stored in the one or more preserved locations of the memory (FIG. 3, 308; ¶[0014]); and
writing the content stored in the one or more preserved locations of the memory back into the one or more locations of the memory to be tested (FIG. 3, 308; ¶[0014]).
Regarding claim 16, Brink teaches the limitations of claim 15.
Brink further teaches the one or more preserved locations of the memory correspond to first or last addresses of the memory (¶[0035] teaches “data from a data block of the flash-memory can be temporarily preserved in a data block memory while a built-in self test is executed for that data block.” If the first or last addresses of that block were excluded, the data therein would not be preserved. ¶[0020] teaches the method can be performed “for each data block of the plurality of N data blocks until a data block test has been performed for all N data blocks,” which includes all data memory addresses.).
Claim Rejections - 35 USC § 103
29. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
30. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
31. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
32. Claims 1-7 are rejected under 35 U.S.C. 103 as being unpatentable over Kuroda (US 20150279484 A1) in view of Fernald (US 20080126728 A1), and further in view of Brink, et al (US 20080209294 A1), hereinafter Brink.
Regarding independent claim 1, Kuroda teaches a memory-testing circuit (FIG. 4; ¶[0010]) in a circuit configurable to perform a test on a memory in the circuit (¶[0058] teaches “For example, the memory test circuit MT1 is incorporated into a semiconductor integrated circuit (for example, a semiconductor chip) along with the register file RF1” and “The register file RF1 is an example of the memory circuit, and the entry ENT is an example of the storing portion”), comprising:
a test controller (FIG. 4, MBIST; ¶[0065]);
a memory data source selection device (FIG. 4, multiplexer/selector SEL4; ¶[0074-0076]) configured to select input data for a write port of the memory (FIG. 4, e.g., WDP0, WDP1; ¶[0074-0076]) from test data outputted from the test controller (FIG. 4, BWDP; ¶[0074-0076]) and data from an output of the memory (FIG. 4, SWDP0, SWDP1; ¶[0074-0076]); and
a memory address source selection device (FIG. 4, multiplexer/selector SEL1; ¶[0069-0071]) configured to select an address for an address port of the memory (FIG. 4, e.g., RAP0..RAP3; ¶[0069-0071]) from an address outputted from the test controller (FIG. 4, BRAP; ¶[0069-0071]).
Kuroda does not teach the memory address source selection device may also select one of one or more preset addresses of the memory.
Fernald teaches in FIG. 12 an address multiplexer (1210) including preset (e.g., USER LIMIT ADD; ¶[0052]) and hard-coded (e.g., RESERVE READ/WRITE LOCK ADD; ¶[0052]) addresses as inputs, and therefore Kuroda and modified by Fernald teaches a memory address source selection device may select one of one or more preset addresses of the memory (see Figure A, which follows).
Kuroda does not teach the test is performed while preserving contents of the memory and the one or more preset addresses corresponding to one or more preserved locations of the memory configured to temporarily store data for one or more locations of the memory to be tested in the test.
Brink teaches the test is performed (FIG. 3, flowchart of a method for testing a memory) while preserving contents of the memory (FIG. 3 and ¶[0047] teach data from a memory area to be tested is temporarily copied to another area during a test and restored to its original location after the test) and the one or more preset addresses (e.g., FIG. 2, 230; FIG. 3, 302; ¶[0047]) corresponding to one or more preserved locations of the memory configured to temporarily store data for one or more locations of the memory to be tested in the test (Referencing FIG. 3, ¶[0047] teaches “In step 301, data from a first data block of a plurality of data blocks of the flash-memory 200 is fetched. In step 302, this fetched data is loaded and stored into the data block memory 230, wherein the fetched data can be stored temporarily. Once the fetched data has been loaded and stored into the data block memory 230, the testing of the first data block of the flash memory 200 can be performed.”).
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Figure A: Kuroda as modified by Fernald
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Fernald into the method of Kuroda to include a multiplexer which is controlled by a control state machine. The ordinary artisan would have been motivated to modify Kuroda in the above manner for the purpose of selecting one of various addresses (Fernald ¶[0052]).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Brink into the method of Kuroda to include temporarily copying data from a memory area to be tested to another area during a test and restoring said data to its original location after the test. The ordinary artisan would have been motivated to modify Kuroda in the above manner for the purpose of executing a test on a flash memory device without damaging the content stored in the flash memory device (Brink ¶[0035]).
Regarding claim 2, Kuroda as modified by Fernald and Brink teaches the limitations of claim 1.
Fernald further teaches the one or more preset addresses of the memory are first or last addresses of the memory (¶[0052] teaches “The reserve read and write/erase lock address is a value that is hard coded in the hardware and is provided as an input to the multiplexer 1210, this being the top of the memory space and a known and fixed value”).
Regarding claim 3, Kuroda as modified by Fernald and Brink teaches the limitations of claim 1.
Brink further teaches the test comprises:
reading content of the one or more locations of the memory to be tested (FIG. 3, 301);
writing the content into the one or more preserved locations of the memory (FIG. 3, 302);
applying a test algorithm to the one or more locations of the memory to be tested (FIG. 3, 303-307);
reading the content stored in the one or more preserved locations of the memory (FIG. 3, 308; ¶[0014]); and
writing the content stored in the one or more preserved locations of the memory back into the one or more locations of the memory to be tested (FIG. 3, 308; ¶[0014]).
Regarding claim 4, Kuroda as modified by Fernald and Brink teaches the limitations of claim 1.
Kuroda further teaches the test controller generates a first selection control signal for the memory data source selection device (FIG. 4, WPSEL; ¶[0068], [0075-0077]) and a second selection control signal for the memory address source selection device (FIG. 4, RPSEL; ¶[0068], [0071-0072]).
Regarding claim 5, Kuroda as modified by Fernald and Brink teaches the limitations of claim 4.
Fernald further teaches the one or more preset addresses have greater than one addresses (¶[0052] and FIG. 12 teach USER LIMIT ADD is “the upper address” of memory 1202, RESERVE READ/WRITE LOCK ADD is “a value that is hard coded,” and USER LOCK ADD is “hard coded as being at a predetermined address”) and a third selection control signal for controlling which of the one or more preset addresses to be selected for a write operation or a read operation (FIG. 12, control signal from Control State Machine 1206 (see also Figure A: Kuroda as modified by Fernald)).
Regarding claim 6, Kuroda as modified by Fernald and Brink teaches the limitations of claim 1.
Kuroda further teaches the data from an output of the memory pass through a comparator, a register, or both before being coupled to an input of the memory data source selection device (FIG. 4, all data to/from the selection devices pass through register file RF1; ¶[0058-0063]).
Regarding claim 7, Kuroda as modified by Fernald and Brink teaches the limitations of claim 1.
Kuroda further teaches the memory is a multi-port memory (e.g., FIG. 4 illustrates write data ports WDP0...WDP1, read data ports RDP0..RDP3, write address ports WAP0..WAP1, and read address ports RAP0..RAP3) and a port having both read and write capability is used to write data into the one or more preserved locations of the memory (FIG. 4, JTAG port; ¶[0066-0067]).
Brink further teaches a port having both read and write capability is used to write data into the one or more preserved locations of the memory (FIG. 2, Data Bus is bidirectional, indicating read/write capability).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRADLEY COON whose telephone number is (571)270-0740. The examiner can normally be reached M-F 8am-5pm (Eastern).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, AMIR ZARABIAN can be reached at (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/B.S.C./Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
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