DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
2. This office action is in response to the Amendment filed on July 20, 2026.
Claims 1, 5, and 8-15 are amended. Claim 16 is canceled. No claims are added.
With the exception of claim 8, Applicant’s amendments to the claims overcome the objections and 112(b) rejections set forth in the previous office action and therefore the objections and 112(b) rejections of claims 1-7 and 15 are withdrawn.
Applicant’s amendments to the claims overcome the rejections under 35 USC § 101 set forth in the previous office action and therefore the rejections under 35 USC § 101 are withdrawn.
Response to Arguments
3. Applicant’s arguments, see pages 8-9, filed July 20, 2026, with respect to claim 15, have been fully considered and are persuasive.
Applicant submits claim 15 is drawn to “reading the content stored in the one or more preserved locations of the memory, wherein the one or more preserved locations of the memory correspond to first or last addresses of the memory” and Brink does not disclose the addresses of the preserved locations of memory. Examiner agrees Brink does not disclose the addresses of the preserved locations of memory and therefore does not teach “wherein the one or more preserved locations of the memory correspond to first or last addresses of the memory.”
4. Applicant’s arguments, see pages 8-9, filed July 20, 2026, with respect to claim 15, have been fully considered and are not persuasive.
Applicant asserts the previous Office Action has identified step 302 of Brink (US 20080209294 A1) as “writing the content into one or more preserved locations of the memory,” which corresponds to data block memory 230 and is outside of the flash memory area; therefore, Brink does not reasonably disclose or suggest, “wherein the one or more preserved locations of the memory correspond to first or last addresses of the memory.”
The instant application defined a “memory” in FIG. 1 and [23] as comprising memory cells, a column address decoder, a row address decoder, driver circuitry, and sense amplifiers. The instant application also states in [25] a memory “device” – which appears to be equated with a “memory” – can have multiple banks. Note the type(s) of memory cells are not specified in the instant application.
Brink FIG. 2 shows a memory device comprising at least memory cells (220, 230, and 240) and an address decoder. Therefore, Brink’s memory device can be seen as analogous to the memory of the instant application and Brink’s cells in 230 cannot be considered “outside” the memory any more than the cells of 220 or 240. Rather, Brink’s cells of 220, 230, and 240 are all within the “memory” as defined by the instant application.
5. Applicant’s arguments, see pages 10-12, filed July 20, 2026, with respect to claim 1, have been fully considered and are not persuasive.
Applicant submits the previous Office Action asserts that it would be obvious to incorporate Fernald's (US 20080126728 A1) method of implementing protection via lock bytes into Kuroda's (US 20150279484 A1) method of testing memory for “the purpose of selecting one of various addresses.” However, the modification of the previous Office Action is not that specific. The modification is to use Fernald’s address-selecting multiplexer as an address-selecting multiplexer in Kuroda’s method.
Applicant further submits with no modification whatsoever, Kuroda discloses selecting one of various addresses and therefore there is no suggestion to modify a reference when the reference already achieves the supposed rationale for modifying. However, according to MPEP § 2145(X)(C), a teaching, suggestion, or motivation to combine references that is found in the prior art is an appropriate rationale for determining obviousness.
Claim Rejections - 35 USC § 112
6. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
7. Claims 8-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 8 recites the limitation, “One or more non-transitory computer-readable media storing computer-executable instructions, when executed by a computer, cause the computer to perform a method, the method comprising:
creating, in a circuit design, a memory-testing circuit…”
Support for this limitation is found in ¶[09] and possibly ¶[20] of the specification. These paragraphs along with the aforementioned limitation appear to teach a method that “creates” (brings into existence) the memory-testing circuit in the circuit design (e.g., the use of schematic capture and printed circuit board layout tools, or perhaps a method that manages the manufacture of the memory-testing circuit in the circuit design). However, the balance of claim 8 and its dependent claims appear to describe a test method using a memory-testing circuit that has already been brought into existence.
Therefore, claim 8 is indefinite and rejected. Claims 9-14 depend on claim 8.
Claim Rejections - 35 USC § 103
8. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
9. Claims 1-7 are rejected under 35 U.S.C. 103 as being unpatentable over Kuroda (US 20150279484 A1) in view of Fernald (US 20080126728 A1), and further in view of Brink, et al (US 20080209294 A1), hereinafter Brink.
Regarding independent claim 1, Kuroda teaches a memory-testing circuit (FIG. 4; ¶[0010]) configurable to perform a test on a memory (¶[0058] teaches “For example, the memory test circuit MT1 is incorporated into a semiconductor integrated circuit (for example, a semiconductor chip) along with the register file RF1” and “The register file RF1 is an example of the memory circuit, and the entry ENT is an example of the storing portion”), comprising:
a test controller (FIG. 4, MBIST; ¶[0065]);
a memory data source selection device (FIG. 4, multiplexer/selector SEL4; ¶[0074-0076]) configured to select input data for a write port of the memory (FIG. 4, e.g., WDP0, WDP1; ¶[0074-0076]) from test data outputted from the test controller (FIG. 4, BWDP; ¶[0074-0076]) and data from an output of the memory (FIG. 4, SWDP0, SWDP1; ¶[0074-0076]); and
a memory address source selection device (FIG. 4, multiplexer/selector SEL1; ¶[0069-0071]) configured to select an address for an address port of the memory (FIG. 4, e.g., RAP0..RAP3; ¶[0069-0071]) from an address outputted from the test controller (FIG. 4, BRAP; ¶[0069-0071]).
Kuroda does not teach the memory address source selection device may also select one of one or more preset addresses of the memory.
Fernald teaches in FIG. 12 an address multiplexer (1210) including preset (e.g., USER LIMIT ADD; ¶[0052]) and hard-coded (e.g., RESERVE READ/WRITE LOCK ADD; ¶[0052]) addresses as inputs, and therefore Kuroda and modified by Fernald teaches a memory address source selection device may select one of one or more preset addresses of the memory (see Figure A, which follows).
Kuroda does not teach the test is performed while preserving contents of the memory and the one or more preset addresses corresponding to one or more preserved locations of the memory configured to temporarily store data for one or more locations of the memory to be tested in the test.
Brink teaches the test is performed (FIG. 3, flowchart of a method for testing a memory) while preserving contents of the memory (FIG. 3 and ¶[0047] teach data from a memory area to be tested is temporarily copied to another area during a test and restored to its original location after the test) and the one or more preset addresses (e.g., FIG. 2, 230; FIG. 3, 302; ¶[0047]) corresponding to one or more preserved locations of the memory configured to temporarily store data for one or more locations of the memory to be tested in the test (Referencing FIG. 3, ¶[0047] teaches “In step 301, data from a first data block of a plurality of data blocks of the flash-memory 200 is fetched. In step 302, this fetched data is loaded and stored into the data block memory 230, wherein the fetched data can be stored temporarily. Once the fetched data has been loaded and stored into the data block memory 230, the testing of the first data block of the flash memory 200 can be performed.”).
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Figure A: Kuroda as modified by Fernald
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Fernald into the method of Kuroda to include a multiplexer which is controlled by a control state machine. The ordinary artisan would have been motivated to modify Kuroda in the above manner for the purpose of selecting one of various addresses (Fernald ¶[0052]).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Brink into the method of Kuroda to include temporarily copying data from a memory area to be tested to another area during a test and restoring said data to its original location after the test. The ordinary artisan would have been motivated to modify Kuroda in the above manner for the purpose of executing a test on a flash memory device without damaging the content stored in the flash memory device (Brink ¶[0035]).
Regarding claim 3, Kuroda as modified by Fernald and Brink teaches the limitations of claim 1.
Brink further teaches the test comprises:
reading content of the one or more locations of the memory to be tested (FIG. 3, 301);
writing the content into the one or more preserved locations of the memory (FIG. 3, 302);
applying a test algorithm to the one or more locations of the memory to be tested (FIG. 3, 303-307);
reading the content stored in the one or more preserved locations of the memory (FIG. 3, 308; ¶[0014]); and
writing the content stored in the one or more preserved locations of the memory back into the one or more locations of the memory to be tested (FIG. 3, 308; ¶[0014]).
Regarding claim 4, Kuroda as modified by Fernald and Brink teaches the limitations of claim 1.
Kuroda further teaches the test controller generates a first selection control signal for the memory data source selection device (FIG. 4, WPSEL; ¶[0068], [0075-0077]) and a second selection control signal for the memory address source selection device (FIG. 4, RPSEL; ¶[0068], [0071-0072]).
Regarding claim 5, Kuroda as modified by Fernald and Brink teaches the limitations of claim 4.
Fernald further teaches the one or more preset addresses have more than one addresses (¶[0052] and FIG. 12 teach USER LIMIT ADD is “the upper address” of memory 1202, RESERVE READ/WRITE LOCK ADD is “a value that is hard coded,” and USER LOCK ADD is “hard coded as being at a predetermined address”) and a third selection control signal for controlling which of the one or more preset addresses is selected for a write operation or a read operation (FIG. 12, control signal from Control State Machine 1206 (see also Figure A: Kuroda as modified by Fernald)).
Regarding claim 6, Kuroda as modified by Fernald and Brink teaches the limitations of claim 1.
Kuroda further teaches the data from an output of the memory pass through a comparator, a register, or both before being coupled to an input of the memory data source selection device (FIG. 4, all data to/from the selection devices pass through register file RF1; ¶[0058-0063]).
Regarding claim 7, Kuroda as modified by Fernald and Brink teaches the limitations of claim 1.
Kuroda further teaches the memory is a multi-port memory (e.g., FIG. 4 illustrates write data ports WDP0...WDP1, read data ports RDP0..RDP3, write address ports WAP0..WAP1, and read address ports RAP0..RAP3) and a port having both read and write capability is used to write data into the one or more preserved locations of the memory (FIG. 4, JTAG port; ¶[0066-0067]).
Brink further teaches a port having both read and write capability is used to write data into the one or more preserved locations of the memory (FIG. 2, Data Bus is bidirectional, indicating read/write capability).
10. Claims 8 and 10-14 are rejected under 35 U.S.C. 103 as being unpatentable over Kleveland, et al (US 20130173970 A1), hereinafter Kleveland, in view of Brink, et al (US 20080209294 A1), hereinafter Brink, and further in view of Kuroda (US 20150279484 A1).
Regarding independent claim 8, Kleveland teaches one or more non-transitory computer-readable media storing computer-executable instructions, when executed by a computer, cause the computer to perform a method (¶[0139]), the method comprising:
creating, in a circuit design, a memory-testing circuit configurable to perform a test on a memory in the circuit design (e.g., FIG. 2B, BBISTM 350-B, ARB 300; ¶[0056]).
Kleveland does not teach the test if performed while preserving contents of the memory.
Brink teaches the test is performed (FIG. 3, flowchart of a method for testing a memory) while preserving contents of the memory (FIG. 3 and ¶[0047] teach data from a memory area to be tested is temporarily copied to another area during a test and restored to its original location after the test).
Kleveland further teaches the memory-testing circuit including,
a test controller (e.g., FIG. 2B, BBISTM 350-B; ¶[0056]),
Kleveland does not clearly teach a memory data source selection device configured to select input data for a write port of the memory from test data outputted from the test controller and data from an output of the memory.
Kuroda teaches a memory data source selection device (FIG. 4, multiplexer/selector SEL4; ¶[0074-0076]) configured to select input data for a write port of the memory (FIG. 4, e.g., WDP0, WDP1; ¶[0074-0076]) from test data outputted from the test controller (FIG. 4, BWDP; ¶[0074-0076]) and data from an output of the memory (FIG. 4, SWDP0, SWDP1; ¶[0074-0076]).
Kleveland further teaches a memory address source selection device (FIG. 2A, ARB 300; FIG. 3A; ¶[0069]) configured to select an address for an address port of the memory (FIG. 3A; ¶[0069]) from an address outputted from the test controller (FIG. 3A, “FROM BBIST”) and one of one or more preset addresses of the memory (FIG. 3A, eFUSE MAP ADDR, selected by MUX 310; ¶[0069]).
Brink further teaches the one or more preset addresses (e.g., FIG. 2, 230; FIG. 3, 302; ¶[0047]) corresponding to one or more preserved locations of the memory configured to temporarily store data for one or more locations of the memory to be tested in the test (Referencing FIG. 3, ¶[0047] teaches “In step 301, data from a first data block of a plurality of data blocks of the flash-memory 200 is fetched. In step 302, this fetched data is loaded and stored into the data block memory 230, wherein the fetched data can be stored temporarily. Once the fetched data has been loaded and stored into the data block memory 230, the testing of the first data block of the flash memory 200 can be performed.”).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Brink into the method of Kleveland to include temporarily copying data from a memory area to be tested to another area during a test and restoring said data to its original location after the test. The ordinary artisan would have been motivated to modify Kleveland in the above manner for the purpose of executing a test on a flash memory device without damaging the content stored in the flash memory device (Brink ¶[0035]).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Kurdoa into the method of Kleveland to include a memory data source selection device. The ordinary artisan would have been motivated to modify Kleveland in the above manner for the purpose of selecting the source for the data to be written to a write port (Kuroda ¶[0076-0077]).
Regarding claim 10, Kleveland as modified by Brink and Kuroda teaches the limitations of claim 8.
Brink further teaches the test comprises:
reading content of the one or more locations of the memory to be tested (FIG. 3, 301);
writing the content into the one or more preserved locations of the memory (FIG. 3, 302);
applying a test algorithm to the one or more locations of the memory to be tested (FIG. 3, 303-307);
reading the content stored in the one or more preserved locations of the memory (FIG. 3, 308; ¶[0014]); and
writing the content stored in the one or more preserved locations of the memory back into the one or more locations of the memory to be tested (FIG. 3, 308; ¶[0014]).
Regarding claim 11, Kleveland as modified by Brink and Kuroda teaches the limitations of claim 8.
Kuroda further teaches the test controller generates a first selection control signal for the memory data source selection device (FIG. 4, WPSEL; ¶[0068], [0075-0077]) and a second selection control signal for the memory address source selection device (FIG. 4, RPSEL; ¶[0068], [0071-0072]).
Regarding claim 12, Kleveland as modified by Brink and Kuroda teaches the limitations of claim 11.
Kleveland further teaches the one or more preset addresses have more than one addresses (¶[0069] teaches “the addresses of both existing in eFUSE MAP ADDR 303”) and the test controller generates a third selection control signal (FIG. 2B, multiple control signals from BBISTM 350-B to ARB 300) for controlling which of the one or more preset addresses is selected for a write operation (¶[0071] teaches target memory under test (TMUT) may be selected for write) or a read operation (¶[0066] teaches a portion of memory may be selected for read).
Regarding claim 13, Kleveland as modified by Brink and Kuroda teaches the limitations of claim 8.
Kuroda further teaches the data from an output of the memory pass through a comparator, a register, or both before being coupled to an input of the memory data source selection device (FIG. 4, all data to/from the selection devices pass through register file RF1; ¶[0058-0063]).
Regarding claim 14, Kleveland as modified by Brink and Kuroda teaches the limitations of claim 8.
Kuroda further teaches the memory is a multi-port memory (e.g., FIG. 4 illustrates write data ports WDP0...WDP1, read data ports RDP0..RDP3, write address ports WAP0..WAP1, and read address ports RAP0..RAP3) and a port having both read and write capability is used to write data into the one or more preserved locations of the memory (FIG. 4, JTAG port; ¶[0066-0067]).
Brink further teaches a port having both read and write capability is used to write data into the one or more preserved locations of the memory (FIG. 2, Data Bus is bidirectional, indicating read/write capability).
Allowable Subject Matter
11. Claim 15 is allowed.
12. Claims 2 and 9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
13. The following is a statement of reasons for the indication of allowable subject matter.
Regarding claim 2, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach or suggest the claimed limitation of wherein the one or more preset addresses of the memory are first or last addresses of the memory.
Regarding claim 9, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach or suggest the claimed limitation of wherein the one or more preset addresses of the memory are first or last addresses of the memory.
Regarding claim 15, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach or suggest the claimed limitation of wherein the one or more preserved locations of the memory correspond to first or last addresses of the memory.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRADLEY COON whose telephone number is (571)270-0740. The examiner can normally be reached M-F 8am-5pm (Eastern).
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/B.S.C./Examiner, Art Unit 2827
/AMIR ZARABIAN/ Supervisory Patent Examiner, Art Unit 2827
Prosecution Insights