DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
The instant application claim of the priority date of 03/10/2022 of the foreign application JP 2022-037203 is noted and entered. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/20/2024 was filed after the mailing date of the application on 08/20/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 7-11 and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ishii et al, US 20200227452 A1 (Ishii).
Regarding claim 1; Ishii teaches a solid-state imaging device (Ishii: Fig (1): 100) comprising:
a semiconductor substrate (160) on which a photoelectric conversion element (120) is formed; and
a plurality of layers (170 = 172+174+176+178; 182; 184; 186) including a first transparent dielectric layer (178+182+184+186)),
a semiconductor layer (174+176), and
a second transparent dielectric layer (172) in order from a side of the semiconductor substrate (160).
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Regarding claim 7; Ishii teaches all the limitations of the solid-state imaging device according to claim 1.
Further, Ishii teaches wherein the semiconductor layer (Ishii: Fig (1): 174+176) includes one of p-Si ([0036]: “…In some embodiments, the refractive pattern 174 may include polysilicon”; in the instant application in paragraph [0034] it is disclosed that polysilicon is referred to as p-Si) or a-Si.
Regarding claim 8; Ishii teaches all the limitations of the solid-state imaging device according to claim 1
Further, Ishii teaches wherein the second transparent dielectric layer (Ishii: Fig (1): 172) includes one of SiO2 or a transparent dielectric material having a higher refractive index than SiO2 ([0035]: “…In some embodiments, the first anti-reflective layer 172 may include an insulating material, for example, silicon oxide, silicon nitride, silicon oxynitride, or a low-k dielectric material, such as SiCN or SiCO.”).
Regarding claim 9; Ishii teaches all the limitations of the solid-state imaging device according to claim 1.
Further, Ishii teaches wherein the second transparent dielectric layer (Ishii: Fig (1): 172) includes a transparent dielectric material ([0035]: “…In some embodiments, the first anti-reflective layer 172 may include an insulating material, for example,… silicon nitride…”) having a refractive index not lower than 1.7 (the refractive index of silicon nitride has a value between 1.9 and 2.2).
Regarding claim 10; Ishii teaches all the limitations of the solid-state imaging device according to claim 1
Ishii teaches wherein the second transparent dielectric layer (Ishii: Fig (1): 172) includes one of Nb2O5, Ta2O5, TiO2, HfO2, or ZrO2 ([0035]: “… The first anti-reflective layer 172 may include metal oxide, for example, hafnium oxide, aluminum oxide, or tantalum oxide.”).
Regarding claim 11; Ishii teaches all the limitations of the solid-state imaging device according to claim 1.
Ishii teaches wherein the first transparent dielectric layer (Ishii: Fig (1): 178+182+184+186) includes a multilayer film in which a plurality of films is stacked (films 178, 182 and 184 are stacked on top of one another).
Regarding claim 19; Ishii teaches all the limitations of the solid-state imaging device according to claim 1
Further, Ishii teaches wherein the plurality of layers (Ishii: Fig (1): 178+182+184+186) includes a microlens layer (186) on an opposite side from a side of the semiconductor layer (174+176) of the second transparent dielectric layer (172).
Regarding claim 20; Ishii teaches all the limitations of an electronic apparatus (Ishii: Abstract) comprising the solid- state imaging device according to claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claims 2-6 are rejected under 35 U.S.C. 103 as being unpatentable over Ishii et al, US 20200227452 A1 (Ishii) in view of Okabe et al, US 20120138999 A1 (Okabe).
Regarding claim 2; Ishii teaches all the limitations of the solid-state imaging device according to claim 1.
However, Ishii does not teach wherein a thickness of the semiconductor layer is 1/2 or less of a total thickness of the first and second transparent dielectric layers.
Okabe teaches wherein a thickness of the semiconductor layer (Okabe: Fig (4): 150b; [0079]: “… The thickness of the well layer 150b may be the thickness by which quantum effects can be obtained, for example, 1 nm to 10 nm,…”) is 1/2 or less of a total thickness of the first (140b; [0074]: “… The n-cladding layer 140b can be formed of AlGaN, GaN, GaInN and so on.” – these materials are transparent at these quoted thicknesses - And [0075]: “The thickness of the n-cladding layer 140b is not particularly limited, but preferably in a range of 0.005 .µ.m (= 5 nm) to 0.5 .µ.m (= 500 nm), and more preferably in a range of 0.005 .µ.m (= 5 nm) to 0.1 .µ.m (= 100 nm)) and second (160a; [0084] It is preferable that the p-cladding layer 160a is composed of such AlGaN in terms of confinement of carriers within the light-emitting layer 150. The thickness of the p-cladding layer 160a is not particularly limited, but preferably 1 nm to 400 nm, and more preferably 5 nm to 100 nm.”) transparent dielectric layers (the range of thicknesses possible for the dielectric layer can be clearly seen to be half or less than the total thickness of the first and second transparent dielectric layers).
Ishii and Okabe are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to one of ordinary skill in the art to modify Ishii by constructing the transparent layers and the semiconductor layers at the thicknesses disclosed in Okabe to improve the protection of the device while maintaining its small size thus leading to a more reliable and better performing device. And while the range of thicknesses disclosed in Okabe is not identical to the one cited in the instant claim, MPEP 2144.05(I) states: “[A] prior art reference that discloses a range encompassing a somewhat narrower claimed range is sufficient to establish a prima facie case of obviousness." In re Peterson, 315 F.3d 1325, 1330, 65 USPQ2d 1379, 1382-83 (Fed. Cir. 2003).
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Regarding claim 3; Ishii in view of Okabe teaches all the limitations of the solid-state imaging device according to claim 2.
However, Ishii does not teach wherein the semiconductor layer has a thickness of at least 2 nm but not greater than 10 nm.
Okabe teaches wherein the semiconductor layer (Okabe: Fig (4): 150b) has a thickness of at least 2 nm but not greater than 10 nm ([0079]: “… The thickness of the well layer 150b may be the thickness by which quantum effects can be obtained, for example, 1 nm to 10 nm,…”).
Ishii and Okabe are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Ishii by constructing the semiconductor layer in the thickness ranges disclosed in Okabe to minimize the size of the device thus allowing for integrating more devices on the chip which leads to higher performance of the device. And while the range of thicknesses disclosed in Okabe is not identical to the one cited in the instant claim, MPEP 2144.05(I) states: “[A] prior art reference that discloses a range encompassing a somewhat narrower claimed range is sufficient to establish a prima facie case of obviousness." In re Peterson, 315 F.3d 1325, 1330, 65 USPQ2d 1379, 1382-83 (Fed. Cir. 2003).
Regarding claim 4; Ishii in view of Okabe teaches all the limitations of the solid-state imaging device according to claim 2.
Ishii does not teach wherein the first transparent dielectric layer has a thickness of at least 5 nm but not greater than 20 nm.
Okabe teaches wherein the first transparent dielectric layer (Okabe: Fig (4): 140b) has a thickness of at least 5 nm but not greater than 20 nm ([0074]: “… The n-cladding layer 140b can be formed of AlGaN, GaN, GaInN and so on.” – these materials are transparent in the ranges of thicknesses disclosed - And [0075]: “The thickness of the n-cladding layer 140b is not particularly limited, but preferably in a range of 0.005 .µ.m (= 5 nm) to 0.5 .µ.m (= 500 nm), and more preferably in a range of 0.005 .µ.m (= 5 nm) to 0.1 .µ.m (= 100 nm)).
Ishii and Okabe are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Ishii by constructing the first transparent layer in the thickness ranges disclosed in Okabe to minimize the size of the device thus allowing for integrating more devices on the chip which leads to higher performance of the device. And while the range of thicknesses disclosed in Okabe is not identical to the one cited in the instant claim, MPEP 2144.05(I) states: “[A] prior art reference that discloses a range encompassing a somewhat narrower claimed range is sufficient to establish a prima facie case of obviousness." In re Peterson, 315 F.3d 1325, 1330, 65 USPQ2d 1379, 1382-83 (Fed. Cir. 2003).
Regarding claim 5; Ishii in view of Okabe teaches all the limitations of the solid-state imaging device according to claim 2
Ishii does not teach wherein the second transparent dielectric layer has a thickness of at least 15 nm but not greater than 60 nm.
Okabe teaches wherein the second transparent dielectric layer (Okabe: Fig (4): 160a) has a thickness of at least 15 nm but not greater than 60 nm ([0084] It is preferable that the p-cladding layer 160a is composed of such AlGaN in terms of confinement of carriers within the light-emitting layer 150. The thickness of the p-cladding layer 160a is not particularly limited, but preferably 1 nm to 400 nm, and more preferably 5 nm to 100 nm.”).
Ishii and Okabe are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Ishii by constructing the second transparent layer in the thickness ranges disclosed in Okabe to minimize the size of the device thus allowing for integrating more devices on the chip which leads to higher performance of the device. And while the range of thicknesses disclosed in Okabe is not identical to the one cited in the instant claim, MPEP 2144.05(I) states: “[A] prior art reference that discloses a range encompassing a somewhat narrower claimed range is sufficient to establish a prima facie case of obviousness." In re Peterson, 315 F.3d 1325, 1330, 65 USPQ2d 1379, 1382-83 (Fed. Cir. 2003).
Regarding claim 6; Ishii in view of Okabe teaches all the limitations of the solid-state imaging device according to claim 2.
However, Ishii does not teach wherein a total thickness of the first transparent dielectric layer, the semiconductor layer, and the second transparent dielectric layer is at least 20 nm but not greater than 80 nm.
Okabe teaches wherein a total thickness of the first transparent dielectric layer (Okabe: Fig (4): 140b), the semiconductor layer (150b), and the second transparent dielectric layer (160b) is at least 20 nm but not greater than 80 nm (adding values from the ranges of thickness of the three different layers disclosed in paragraphs [0074], [0079] and [0084] and explicitly quoted in claims 3-5 above results in a combination that is in the range of 11 nm to 610 nm).
Ishii and Okabe are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Ishii by constructing the first transparent layer, the semiconductor layer and the second transparent layer to have the total thickness in the range disclosed in Okabe to minimize the size of the device thus allowing for integrating more devices on the chip which leads to higher performance of the device. And while the range of thicknesses disclosed in Okabe is not identical to the one cited in the instant claim, MPEP 2144.05(I) states: “[A] prior art reference that discloses a range encompassing a somewhat narrower claimed range is sufficient to establish a prima facie case of obviousness." In re Peterson, 315 F.3d 1325, 1330, 65 USPQ2d 1379, 1382-83 (Fed. Cir. 2003).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Ishii et al, US 20200227452 A1 (Ishii) in view of Katoh et al, US 20170235173 A1 (Katoh).
Regarding claim 12; Ishii teaches all the limitations of the solid-state imaging device according to claim 11.
Ishii teaches wherein the plurality of films (Ishii: Fig (1): 178+182+184+186) includes an A12O3 film and a Ta2O5 film in order ([0039]: “… The second anti-reflective layer 178 may include metal oxide, for example, hafnium oxide, aluminum oxide, or tantalum oxide.”) from a side of the semiconductor substrate (120).
Ishii does not disclose that both A12O3 film and a Ta2O5 film in order from a side of the semiconductor substrate.
However, Katoh discloses both A12O3 film and a Ta2O5 film (Katoh: Fig (1): 13) in order from a side of the semiconductor substrate (10; [0113]: "... The first insulating layer 13 is, for example, a silicon oxide (SiO.sub.x) film, a silicon nitride (SiN.sub.x) film, a silicon oxynitride (SiO.sub.xN.sub.y, x>y) film, a silicon nitroxide (SiN.sub.xO.sub.y, x>y) film, an aluminum oxide film or a tantalum oxide film, or a multilayer film thereof.").
Ishii and Katoh are considered analogous art. Thus, it would have been obvious, to one of ordinary skill in the art, to modify Ishii by introducing the second film to improve the insulation of the device and thus reduce the possibilities of a short circuit occurring leading to a more reliable device.
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Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Ishii et al, US 20200227452 A1 (Ishii) in view of Komitov et al, US 20220365382 A1 (Komitov).
Regarding claim 13; Ishii teaches all the limitations of the solid-state imaging device according to claim 1.
However, Ishii does not teach wherein a negative bias is applied to the semiconductor layer.
However, Komitov teaches wherein a negative bias is applied to the semiconductor layer (Lachezar: Fig (2): 19; 21; [0115]: “… The top of these PVUs are covered with electrons 21 and holes 22 conductive layers, respectively. As a result, a photo-generate potential difference (bias), defined as photo-voltage Vph, appears between the conductive layers (electrodes) 21 and 22”, as can be seen in Fig (2) the transparent layer 21 covered with electrons which makes it a source of negative bias potential is in contact with the semiconductor layer 19).
Ishii and Komitov are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Ishii by constructing a negative bias source applied to the semiconductor layer as disclosed in Komitov to improve the collection of the electric signal in the device leading to a better performing device.
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Claims 17 are rejected under 35 U.S.C. 103 as being unpatentable over Ishii et al, US 20200227452 A1 (Ishii) in view of Sizukuisi, US 20100066883 A1 (Sizukuisi).
Regarding claim 17; Ishii teaches all the limitations of the solid-state imaging device according to claim 1.
Ishii teaches wherein the plurality of layers (Ishii: Fig (1): 178+182+184+186) includes a color filter layer (184) in which a plurality of color filters is arranged in an in-plane direction on an opposite side from a side of the semiconductor layer of the second transparent dielectric layer, and the second transparent dielectric layer has a plurality of regions that correspond to the plurality of color filters and have different thicknesses.
Ishii does not teach a plurality of color filters is arranged in an in-plane direction on an opposite side from a side of the semiconductor layer of the second transparent dielectric layer, and the second transparent dielectric layer has a plurality of regions that correspond to the plurality of color filters and have different thicknesses.
Sizukuisi teaches a plurality of color filters (Sizukuisi: Fig (2): 67; B, G) is arranged in an in-plane direction on an opposite side (Top Side) from a side of the semiconductor layer (50) of the second transparent dielectric layer (66), and the second transparent dielectric layer (66) has a plurality of regions that correspond to the plurality of color filters (67; B, G) and have different thicknesses (T1 and T2).
Ishii and Sizukuisi are considered analogous art. Thus it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Ishii by introducing the different thicknesses of the dielectric layer as disclosed in Sizukuisi to decrease the thickness of the device leading to the ability of increasing the density of devices per chip which improves the performance of the device.
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Claims 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Ishii et al, US 20200227452 A1 (Ishii) In view of Martin et al, US 20190123033 A1 (Martin).
Regarding claim 14; Ishii teaches all the limitations of the solid-state imaging device according to claim 1
However, Ishii does not teach further comprising a light-blocking film in contact with the semiconductor layer on an opposite side from a side of the first transparent dielectric layer, wherein a negative bias is applied to the light- blocking film.
Martin teaches further comprising a light-blocking film (Martin: Annotated Fig (2) shared in this OA: 54) in contact with the semiconductor layer (28) on an opposite side from a side of the first transparent dielectric layer (26, while Martin does not explicitly specify that layer 26 is transparent, given the purpose of layer 26 is to pass light through it for the device to function properly, it is assumed that layer 26 is transparent. This assumption is supported by both Fig (2) and paragraph [0054] of Martin: “[0054] Reflective P-metal electrodes 44 (anode electrodes) are formed on the P-type layer 26…”, where the need for a reflective anode to be formed over 26 is to keep the light inside the device indicating that light can escape through 26.), wherein a negative bias is applied to the light- blocking film ([0057]: “A reflective N-metal 54 (cathode electrode) is then deposited in the trenches between the hexagonal pixels to electrically contact a large vertical sidewall area of the N-type layer 30.”).
Ishii and Martin are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Ishii by constructing a light blocking film that has a negative voltage applied to it as disclosed in Martin to improve the retention of the light signal inside the device leading to a better performing device.
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Regarding claim 15; Ishii teaches all the limitations of the solid-state imaging device according to claim 1.
Ishii does not teach wherein a trench is formed in a surface of the semiconductor substrate on a light incident side, and part of the first transparent dielectric layer, part of the semiconductor layer, and part of the second transparent dielectric layer are disposed in the trench.
Martin teaches wherein a trench (Martin: Fig (1): Area inside 12; [0055]: “After the LED semiconductor layers are formed, they are masked and etched (e.g., by RIE) to form hexagonal trenches around each pixel area. These trenches form pillars of the semiconductor layers in a honeycomb pattern.”) is formed in a surface of the semiconductor substrate (Substrate) on a light incident side, and part of the first transparent dielectric layer (Annotated Fig (2) shared in this OA: 26), part of the semiconductor layer (28), and part of the second transparent dielectric layer (30) are disposed in the trench (while the layers 26, 28 and 30 are not explicitly stated as transparent their composition and function are to allow light to travel through them and thus they can be assumed to be transparent. This assumption is supported by both Fig (2) and paragraph [0054] of Martin: “[0054] Reflective P-metal electrodes 44 (anode electrodes) are formed on the P-type layer 26…”, where the need for a reflective anode to be formed over 26 is to keep the light inside the device indicating that light can escape through 26.).
Ishii and Martin are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person of ordinary skill in the art, to modify Ishii by constructing the trenches as disclosed in Martin to provide more protection and isolation for the device components leading to a more reliable device.
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Regarding claim 16; Ishii in view of Martin teaches all the limitations of the solid-state imaging device according to claim 15.
Ishii does not teach wherein a negative bias is applied to the semiconductor layer.
Martin teaches wherein a negative bias is applied to the semiconductor layer (Martin: Annotated Fig (2) shared in this OA: 28; [0057]: “A reflective N-metal 54 (cathode electrode) is then deposited in the trenches between the hexagonal pixels to electrically contact a large vertical sidewall area of the N-type layer 30.”, since 54 applies negative (cathode) voltage to the semiconductor layer 30 and 30 is in contact with the semiconductor layer 28, then negative (cathode) voltage is applied to the semiconductor layer 28).
Ishii and martin are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Ishii by applying a negative potential as disclosed in Martin to improve signal collection and thus lead to a better performing device.
Claims 17 are rejected under 35 U.S.C. 103 as being unpatentable over Ishii et al, US 20200227452 A1 (Ishii) in view of Sizukuisi, US 20100066883 A1 (Sizukuisi) in further view of Takiguchi et al, WO 2020209109 A1 (Takiguchi).
Regarding claim 18; Ishii in view of Sizukuisi teaches all the limitations of the solid-state imaging device according to claim 17
However, Ishii in view of Sizukuisi does not teach wherein, among the plurality of regions, the region corresponding to the color filter having a longer transmission wavelength is thicker.
Takiguchi teaches wherein, among the plurality of regions, the region corresponding to the color filter (Takiguchi: Fig (2A): 12; 23; 33) having a longer transmission wavelength is thicker (see Page: 11 Lines: 27-31 of the translated copy of Takiguchi attached to this OA: “ (however, λ .sub.1 ′ <λ .sub.2 ′ <λ .sub.3 ′). Is equipped with. And Satisfy T .sub.1 <T .sub.2 ≤ T .sub.3”).
Ishii in view of Sizukuisi and Takiguchi are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Ishii in view of Sizukuisi by constructing the color filter layer such that the thicker portions correspond to the longer wavelength as disclosed in Takiguchi to improve the efficiency of the color filtration layer leading to a more reliable device.
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Conclusion
Prior art made of record but not relied upon is considered pertinent to applicant’s disclosure:
Honishi et al, US 20210184066 A1 (Honishi): discloses two transparent layers with a semiconductor layer stacked between them.
Arao et al, US 6110347 A (Arao); discloses two transparent layers with a semiconductor layer stacked between them.
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/M.K./Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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