Prosecution Insights
Last updated: October 21, 2026
Application No. 18/840,093

Micro LED Display Device and Method for Manufacturing Micro LED Display Device

Non-Final OA §103
Filed
Aug 21, 2024
Priority
Feb 22, 2022 — RE 10-2022-0022907 +1 more
Examiner
HARBOTTLE, CHARLOTTE ELIZABETH
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Korea Institute Of Energy Technology
OA Round
1 (Non-Final)
100%
Grant Probability
Favorable
1-2
OA Rounds
5m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 100% — above average
100%
Career Allowance Rate
1 granted / 1 resolved
+32.0% vs TC avg
Minimal +0% lift
Without
With
+0.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
15 currently pending
Career history
13
Total Applications
across all art units

Statute-Specific Performance

§103
55.2%
+15.2% vs TC avg
§102
20.7%
-19.3% vs TC avg
§112
24.1%
-15.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Drawings The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: 140, which is interpreted to represent the pads. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Objections Claims 1, 4-9, & 11-15 objected to because of the following informalities: Within claims 1, 4-9, & 11-15 there are indentions after the corrections made within the abstract that leaves out of place gaps within the claims which should be removed. The removal of the word “includes” in claims 1, 4-9, & 11-15 leaves the claims grammatically incorrect. This change should be corrected. Appropriate correction is required. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-3, 6, 11, & 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Peng et al. (US 20170104009 A1). Regarding claim 1, Peng et al. teaches a micro LED display device comprising: a driving substrate a first pad and a second pad (Fig 5 shows an array substrate, 200, which includes two pads, 204 being the first pad and 205 being the second pad); and a micro LED a light-emitting structure in which an n-type semiconductor layer, an active layer, and a p-type semiconductor layer are stacked (Fig 5 shows a LED structure which contains two active layers, 502 and 504, with an active layer, 503, in between them. Paragraph 0044 describes that first semiconductor layer, 502, is a N-type layer and the second semiconductor layer, 504, is a P-type layer), an n-type pad electrically connecting the n-type semiconductor layer to the first pad, and a p-type pad electrically connecting the p-type semiconductor layer to the second pad (Paragraph 0044 states that a n-type pad, 506, is electrically connected to the N-type semiconductor layer, 502, and that a p-type pad, 505, is electrically connected to the P-type semiconductor layer, 504), wherein one of the n-type pad and p-type pad is provided on a side surface of the light-emitting structure (Fig 5 shows the N-type pad, 506, on the side surface of the light-emitting structure, 500). Peng et al. does not explicitly teach the first and second pad being connected to different potentials (Paragraph 0046 does describe that the first pad, 204, and the second pad, 205, form two different electrical paths, which cause different electrical connections but does not mention the potentials). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the first and second pad in Peng et al. to have different potentials since they are already two different paths and giving these two paths different potentials would allow for different uses between the electrical paths and increase the overall functionality of the system. Regarding claim 2, Peng et al. teaches the other of the n-type pad and the p-type pad is provided on a front or rear surface of the light-emitting structure (Fig 5 shows that the p-type pad, 505, is on the rear surface of the light-emitting structure, 500). Regarding claim 3, Peng et al. teaches one of the n-type pad and the p-type pad provided on the side surface of the light-emitting structure is provided at a higher position than the other of the n-type pad and the p-type pad provided on the front or rear surface of the light-emitting structure (Fig 5 shows that the N-type pad, 506, on the side surface of the light-emitting structure, 500, is at a higher position than the P-type pad, 505). Regarding claim 6, Peng et al. teaches a passivation layer provided on side surfaces of the active layer and the p-type semiconductor layer (Fig 5 shows an insulating layer, 509, on the side surface of the p-type semiconductor layer, 504, and the active layer, 503. The insulating layer works as a passivation layer, as paragraph 00444 describes the insulating layer protecting the P-type semiconductor layer, 504, and the active layer, 503, by electrically insulating them from the N-type pad, 506). Regarding claim 11, Peng et al. teaches a method for manufacturing a micro LED display device, comprising: preparing a driving substrate a first pad and a second pad (Fig 5 shows an array substrate, 200, which includes two pads, 204 being the first pad and 205 being the second pad); preparing a plurality of micro LEDs a light-emitting structure in which an n-type semiconductor layer, an active layer, and a p-type semiconductor layer are stacked (Fig 5 shows a LED structure which contains two active layers, 502 and 504, with an active layer, 203, in between them. Paragraph 0044 describes that first semiconductor layer, 502, is a N-type layer and the second semiconductor layer, 504, is a P-type layer), an n-type pad electrically connected to the n-type semiconductor layer, and a p-type pad electrically connected to the p-type semiconductor layer (Paragraph 0044 states that a n-type pad, 506, is electrically connected to the N-type semiconductor layer, 502, and that a p-type pad, 505, is electrically connected to the P-type semiconductor layer, 504), one of the n-type pad and the p-type pad being provided on a side surface of the light-emitting structure (Fig 5 shows the N-type pad, 506, on the side surface of the light-emitting structure, 500); and bonding the plurality of micro LEDs to the driving substrate so that one of the n-type pad and the p-type pad provided on the side surface of the light-emitting structure is electrically connected to one of the first pad and the second pad (Paragraph 0046 states that the N-type pad, 506, which is shown to be on the side surface of the LED, 500, in Fig. 5, is electrically connected to the second pad, 205) and the other of the n-type pad and the p-type pad is electrically connected to the other of the first pad and the second pad (Paragraph 0046 states that the P-type pad, 505, is electrically connected to the first pad, 204). Peng et al. does not explicitly teach the first and second pad being connected to different potentials (Paragraph 0046 does describe that the first pad, 204, and the second pad, 205, form two different electrical paths, which cause different electrical connections but does not mention the potentials). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the first and second pad in Peng et al. to have different potentials since they are already two different paths and giving these two paths different potentials would allow for different uses between the electrical paths and increase the overall functionality of the system. Regarding claim 14, Peng et al. teaches an insulating layer having a through-hole provided to expose the first pad and the second pad (Fig 5 shows an insulating layer, 106, which contains a through-hole, 107. Fig 5 shows that within the through hole, 107, both the first pad, 204, and the second pad, 205 are exposed), and Inserting at least a portion of the micro LED into the through-hole corresponding to the first pad or the second pad electrically connected to the n-type pad or the p- type pad provided on a front or rear surface of the light-emitting structure (Paragraph 0046 describes the LED, 500, being mounted on the side wall, 107a, which is in the through-hole, 107. Fig 5 shows that the side of the through hole, 107a, which is the side of the through hole that the LED is being mounted to, is the one that contains the first pad, 204, which is electrically connected to the P-type pad, 505, on the backside surface of the LED). Regarding claim 15, Peng et al. teaches a passivation layer provided on side surfaces of the active layer and the p-type semiconductor layer (Fig 5 shows an insulating layer, 509, on the side surface of the p-type semiconductor layer, 504, and the active layer, 503. The insulating layer works as a passivation layer, as paragraph 00444 describes the insulating layer protecting the P-type semiconductor layer, 504, and the active layer, 503, by electrically insulating them from the N-type pad, 506). Claims 4, 8, & 12 are rejected under 35 U.S.C. 103 as being unpatentable over Peng et al. (US 20170104009 A1) in view of Lutgen et al. (US 20210111319 A1). Regarding claim 4, Peng et al. does not teach a side contact portion extending from the first pad or the second pad electrically connected to one of the n-type pad and the p-type pad provided on the front or rear surface of the light-emitting structure. Lutgen et al. teaches a side contact portion extending from the first pad or the second pad electrically connected to one of the n-type pad and the p-type pad provided on the front or rear surface of the light-emitting structure (Fig 7A shows a contact layer, 790, on the outer side edges of a LED, 700, and a conductive layer, 760. When added to Peng et al., the contact layer would be added to the outer edges of the LED, leaving it between the N-type pad, 508, and the second pad, 205). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Peng et al. to include a side contact portion between the second pad and the n-type pad, as taught in Lutgen et al., because a shared contact area between the two pads would help minimize the interface resistance between the LED’s internal electrodes and the external circuit, allowing for more efficient current flow. Regarding claim 8, Peng et al., as modified, teaches one of the n-type pad and the p-type pad provided on the side surface of the light-emitting structure and a side contact portion each include a material for forming a eutectic mixture during a bonding process (As the material needed for eutectic bonding is for each of the layers to contain metal, both the N-type pad on the side structure and the side contact achieve that. Paragraph 0039 states that the N-type pad, 406, contains a magnetic material. Paragraph 0033 then lists the possible magnetic materials that the pad contains, which contain several metals. The contact layer, which was taught in by Lutgen et al. in claim 4, also contains material that is capable of being formed into a eutectic mixture. Paragraph 0116 describes that the contact layer, 790, is made from metal. Therefore, the contact portion contains materials that would allow it to form a eutectic mixture). Regarding claim 12, Peng et al. does not teach the formation of a side contact portion extending from the first pad or the second pad electrically connected to one of the n-type pad and the p-type pad provided on the side surface of the light-emitting structure toward one of the n-type pad and the p-type pad provided on the side surface of the light-emitting structure Lutgen et al. teaches forming a side contact portion extending from the first pad or the second pad electrically connected to one of the n-type pad and the p-type pad provided on the side surface of the light-emitting structure toward one of the n-type pad and the p-type pad provided on the side surface of the light-emitting structure (Fig 7A shows a contact layer, 790, on the outer side edges of a LED, 700, and a conductive layer, 760. When added to Peng et al., the contact layer would be added to the outer edges of the LED, leaving it between the N-type pad, 508, and the second pad, 205). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Peng et al. to include a side contact portion between the second pad and the n-type pad, as taught in Lutgen et al., because a shared contact area between the two pads would help minimize the interface resistance between the LED’s internal electrodes and the external circuit, allowing for more efficient current flow. Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Peng et al. (US 20170104009 A1) in view of Kim et al. (US 20210320231 A1). Regarding claim 5, Peng et al. teaches a plurality of driving thin film transistors (TFTs) individually driving ON/OFF of the micro LEDs provided in plurality (Paragraph 0028 describes that at least one of the pixels can include a TFT, 103. The driving thin film transistor is able to drive the micro LEDs ON/OFF); and one of the first pad and the second pad is electrically connected to a source/drain electrode of the driving TFT (Paragraph 0032 states that the first pad, 204, is in electrical contact with the drain electrode, 203e) Peng et al. does not explicitly teach a common voltage interconnection providing a common potential to the plurality of micro LEDs, wherein one of the first pad and the second pad is electrically connected to the common voltage interconnection. Lee et al. teaches a common voltage interconnection providing a common potential to the plurality of micro LEDs, wherein one of the first pad and the second pad is electrically connected to the common voltage interconnection (Paragraph 0090 describes a second alignment voltage applied to a second electrode, REL2, which is equivalent to the second pad, through a connection line, CNL2. Paragraph 0093 states that the second pad, REL2, is electrically connected to each of the light emitting elements, LD. Fig 9 then shows that the connection line, CNE2, is connected to both the first and second light-emitting elements, LD1 and LD2. Therefore, the connection line, CNE2 serves to send a common voltage to the LEDs, LD1 and LD2, and is electrically connected to the second pad, REL2). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Peng et al. to add a common voltage interconnection to send a common potential to the plurality of LEDs through one of the pads, as taught in Lee et all., because it helps to simplify the wiring, helping to simply the manufacturing of the LED display while maintaining power efficiency. Claims 7 is rejected under 35 U.S.C. 103 as being unpatentable over Peng et al. (US 20170104009 A1) in view of Kim et al. (US 20190165208 A1). Regarding claim 7, Peng et al. teaches the p-type pad is provided on the side surface of the light-emitting structure (Paragraph 0044 states that the first semiconductor layer, 502, is a first conductivity while the second semiconductor layer, 504, is a second conductivity layer. Meaning that conductivity of the first semiconductor layer, 502, would be able to be a P-type semiconductor layer. Which would make the side surface pad, 506, a P-type pad) As cited from MPEP 2144.04, in cases in which there is “reversal, duplication, or rearrangement of parts” a prima facie case of obviousness exists. In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950) (Claims to a hydraulic power press which read on the prior art except with regard to the position of the starting switch were held unpatentable because shifting the position of the starting switch would not have modified the operation of the device.); In re Kuhle, 526 F.2d 553, 188 USPQ 7 (CCPA 1975) (the particular placement of a contact in a conductivity measuring device was held to be an obvious matter of design choice). It would have been obvious to one of ordinary skills in the art before the effective filing date of the claimed invention to modify Peng et al. to switch the order of the semiconductor layers in order to have the p-type pad on the side surface because there are two conductivities types in which the side surface pad, 506, can be: N-type or P-type. Therefore, it would have been obvious for one with ordinary skill in the art would try having the side surface pad be a p-type pad. It also would have been obvious because having the p-type pad above the n-type pad allows for the simplification of the current in the p-type region, which reduces current crowding and improves efficiency. Peng et al. does not teach a transparent p-type electrode provided on the p-type semiconductor layer. Kim et al. teaches a transparent p-type electrode provided on the p-type semiconductor layer (Paragraph 0091 describes a light emitting structure in which a second conductivity type semiconductor layer, 113, is a P-type electrode and a transparent electrode layer, 160, is formed on the P-type semiconductor layer, 113). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Peng et al. to add a transparent electrode to the p-type semiconductor layer, as taught in Kim et al., because the transparent electrode layer forms ohmic contact with the P-type semiconductor layer which improves current spreading efficiency along with helping to maintain a predetermined level of transmittance to improve efficiency and brightness of the light emitting diode (Paragraph 0091 of Kim et al.). Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Peng et al. (US 20170104009 A1). Regarding claim 9, Peng et al. teaches an insulating layer having a through-hole provided to expose the first pad and the second pad (Fig 5 shows an insulating layer, 106, which contains a through-hole, 107. Fig 5 shows that within the through hole, 107, both the first pad, 204, and the second pad, 205 are exposed). Peng et al. does not explicitly teach a cross-sectional area of the through-hole corresponding to the first pad or the second pad electrically connected to the n-type pad or the p- type pad provided on the front or rear surface of the light-emitting structure is larger than a cross- sectional area of the light-emitting structure As cited from MPEP 2144.04, in cases in which there is “changes in size/proportion” a prima facie case of obviousness exists. In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Peng et al. to have the cross-sectional area of the through-hole being larger than the cross-sectional area of the LED because having the area of the through hole larger than the LED would make it easier to insert the LED into the through hole, reducing the chance of damaging the LED during the manufacturing process when the LED is placed into the through hole. Claims 10 is rejected under 35 U.S.C. 103 as being unpatentable over Peng et al. (US 20170104009 A1) in view of Herner (US 20190355874 A1). Regarding claim 10, Peng et al. does not explicitly teach an effective cross-sectional area of the micro LED is 100 μm2 or less. Herner teaches an effective cross-sectional area of the micro LED is 100 μm2 or less (Paragraph 0029 states that the LED has an area of less than 100 microns squared). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Peng et al. to have the cross-sectional area 100 microns squared or less, as taught in Herner, because it allows for a smaller form factor, which enables manufacturers to reduce costs and materials while maintaining the same amount of power and performance. Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Peng et al. (US 20170104009 A1) in view of Lutgen et al. (US 20220173159 A1) as applied to claim 12 above, and further in view of Chuang et al. (US 20200357955 A1). Regarding claim 13, Peng et al. does not teach supplying energy so that one of the N-type pad and the P-type pad provided on the side surface of the light-emitting structure and the side contact portion form a eutectic mixture. Chuang et al. teaches supplying energy so that one of the n-type pad and the p-type pad provided on the side surface of the light-emitting structure and the side contact portion form a eutectic mixture (Paragraph 0030 describes attaching the LED to the array substrate by connecting two electrodes through a eutectic process. Paragraph 0044 of Peng et al. describes the N-type pad, 506, which is on the side surface of the LED, as an electrode. Paragraph 102, of Lutgen et al. describes the contact layer, which was taught in for claim 12 as connecting to the N-type pad, as an electrode). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Peng et al., as modified, to have the N-type pad on the side surface of the LED form a eutectic bond with the contact layer because it allows for the emission of a wire-bonding region, which allows for the reduction in the volume of the light-emitting diode to be reduced, which enables manufacturers to reduce costs and materials. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Jeon et al. (US 20220352240 A1) contains a light emitting device that contain a plurality of pads connected to the light-emitting diode. In which a connection electrode is connected to the light-emitting diode through a eutectic bond. Liu et al. (US 20230007967 A1) contains a plurality of light emitting diodes which contains a similar structure to the application, such as a plurality of pads, one of them being a pad connected to one of the semiconductor layers on the side surface. Im et al. (US 12255223 B2) contains a similar structure in which a plurality of pads are electrically connected to the light emitting diode, some on the side surface of the LED. The first and second electrodes contain different potentials. Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLOTTE ELIZABETH HARBOTTLE whose telephone number is (571)270-0644. The examiner can normally be reached Monday-Friday 7:30-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached at (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /C.E.H./Examiner, Art Unit 2818 /JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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Prosecution Timeline

Aug 21, 2024
Application Filed
Oct 13, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
100%
Grant Probability
99%
With Interview (+0.0%)
2y 7m (~5m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1 resolved cases by this examiner. Grant probability derived from career allowance rate.

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