DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Status of the application
This office Action is in response to Applicant's Application filled on 08/21/2024. Claims 1-7, 9-10, 12, 16, 18-22, 24-25 and 27-28 are pending for this examination.
Oath/Declaration
The oath or declaration filed on 08/21/2024 is acceptable.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 02/12/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as failing to set forth the subject matter which the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the applicant regards as the invention.
Regarding Claim 1, The instant claims recite limitation “a base substrate, a plurality of pixel opening areas arranged on the base substrate, at least one planarization layer and at least two conductive layers stacked on the base substrate, wherein one planarization layer is arranged between adjacent conductive layers, and …………the first signal line is electrically connected to the second signal line through the first type of via hole; the signal line for transmitting the power supply voltage signal includes a third signal line and a fourth signal line, and the third signal line is electrically connected to the fourth signal line through the second type of via hole and an orthographic projection of the first type of via hole on the base substrate does not overlap an orthographic projection of the pixel opening area on the base substrate; an orthographic projection of the second type of via hole on the base substrate does not overlap the orthographic projection of the pixel opening area on the base substrate” is not clear because the first signal line is electrically connected to the second signal line through the first type of via hole and the third signal line is electrically connected to the fourth signal line through the second type of via hole, is not defined. In addition, “an orthographic projection of the first type of via hole on the base substrate does not overlap an orthographic projection of the pixel opening area on the base substrate; an orthographic projection of the second type of via hole on the base substrate does not overlap the orthographic projection of the pixel opening area on the base substrate”, is that the plurality of pixel opening areas or only one pixel opening area is not clear. Therefore, the resulting claim is indefinite and is failing to particularly point out and distinctly claim the subject matter. Appropriate corrections defining these limitations within metes and bounds of the claimed invention are required.
Regarding Claim 2, The instant claims recite limitation “wherein the display panel comprises a first conductive layer, a second conductive layer, and a first planarization layer………….. the first planarization layer has the first via hole; the first reference signal line is electrically connected to the first reference connection line through the first via hole” is not clear because claim 1 recites “at least one planarization layer ……….the first planarization layer has the first via hole”, is that same planarization layer or another planarization layer in claim 2. Therefore, the resulting claim is indefinite and is failing to particularly point out and distinctly claim the subject matter. Appropriate corrections defining these limitations within metes and bounds of the claimed invention are required.
Regarding Claim 4, The instant claims recite limitation “the display panel comprises a first conductive layer, a second conductive layer, and a first planarization layer……. the first planarization layer has the second via hole” is not clear because claim 1 recites “at least one planarization layer ……….the first planarization layer has the first via hole”, is that same planarization layer or another planarization layer in claim 4. Therefore, the resulting claim is indefinite and is failing to particularly point out and distinctly claim the subject matter. Appropriate corrections defining these limitations within metes and bounds of the claimed invention are required.
Regarding Claim 7, The instant claims recite limitation “the display panel also includes a semiconductor layer, a first conductive layer, a first planarization layer………. the first planarization layer has the third via hole” is not clear because claim 1 recites “at least one planarization layer ……….the first planarization layer has the first via hole”, is that same planarization layer or another planarization layer in claim 7. Therefore, the resulting claim is indefinite and is failing to particularly point out and distinctly claim the subject matter. Appropriate corrections defining these limitations within metes and bounds of the claimed invention are required.
Regarding Claim 9, The instant claims recite limitation “display panel further includes a semiconductor layer, a first conductive layer, a first planarization layer………. the first planarization layer has the seventh via hole” is not clear because claim 1 recites “at least one planarization layer ……….the first planarization layer has the first via hole”, is that same planarization layer or another planarization layer in claim 9. Therefore, the resulting claim is indefinite and is failing to particularly point out and distinctly claim the subject matter. Appropriate corrections defining these limitations within metes and bounds of the claimed invention are required.
Regarding Claim 10, The instant claims recite limitation “ display panel further includes a semiconductor layer, a first conductive layer, a first planarization layer……… the first planarization layer has the third via hole” is not clear because claim 1 recites “at least one planarization layer ……….the first planarization layer has the first via hole”, is that same planarization layer or another planarization layer in claim 10. Therefore, the resulting claim is indefinite and is failing to particularly point out and distinctly claim the subject matter. Appropriate corrections defining these limitations within metes and bounds of the claimed invention are required.
Claims 2-7, 9-10, 12, 16, 18-22, 24-25 and 27-28 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, because of their dependency status from claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over CAO et al (US 2024/0268187 A1; hereafter CAO).
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Regarding claim 1. CAO first embodiment discloses a display panel comprising a base substrate (Fig. [55], substrate 110, Para [ 0043]), a plurality of pixel opening areas (“each light-emitting element 130 is a region corresponding to an opening of the pixel”, Para [ 0079]) arranged on the base substrate (substrate 110, Para [ 0043]), at least one planarization layer (planarization layer 186, Para [ 0099]) and at least two conductive layers ( first connection electrode 134/ auxiliary electrode 140, Para [0046, 0084], shown in Figure [5,12]) stacked on the base substrate (Fig. [55], substrate 110, Para [ 0043]), wherein one planarization layer (planarization layer 186, Para [ 0099]) is arranged between adjacent conductive layers ( first connection electrode 134/ auxiliary electrode 140, Para [0046, 0084], shown in Figure [5,12]), and the planarization layer (planarization layer 186, Para [ 0099]) has a first type of via hole and a second type of via hole (Fig [5], annotated left and right holes (61), Para [ 0085-0088], and also shown in figure [ 12-13]);
an orthographic projection of the first type of via hole (Fig [5], annotated left hole (61), Para [0085-0088], and also shown in figure [ 12-13]) on the base substrate (Fig. [55], substrate 110, Para [ 0043]) does not overlap an orthographic projection of the pixel opening area (“each light-emitting element 130 is a region corresponding to an opening of the pixel”, Para [ 0079]) on the base substrate (Fig. [55], substrate 110, Para [ 0043]);
an orthographic projection of the second type of via hole (Fig [5], annotated right hole (61), Para [0085-0088], and also shown in figure [ 12-13]) on the base substrate Fig. [55], substrate 110, Para [ 0043]) does not overlap the orthographic projection of the pixel opening area (“each light-emitting element 130 is a region corresponding to an opening of the pixel”, Para [ 0079]) on the base substrate Fig. [55], substrate 110, Para [ 0043]).
But CAO first embodiment does not disclose explicitly the display panel includes a signal line for transmitting a reference voltage signal, and a signal line for transmitting a power supply voltage signal;
the signal line for transmitting the reference voltage signal includes a first signal line and a second signal line;
the first signal line is electrically connected to the second signal line through the first type of via hole;
the signal line for transmitting the power supply voltage signal includes a third signal line and a fourth signal line, and the third signal line is electrically connected to the fourth signal line through the second type of via hole;
However, CAO second embodiment discloses the display panel includes a signal line (scan lines S1/S2, Para [0025]) for transmitting a reference voltage signal (Para [ 0025], power supply line, VDD), and a signal line (Scan lines S3, S4, Para [ 0025]) for transmitting a power supply voltage signal (Para [ 0025], power supply line VSS);
the signal line (scan lines S1/S2, Para [0025]) for transmitting the reference voltage signal (Para [ 0025], power supply line, VDD includes a first signal line and a second signal line (scan lines S1/S2, Para [0025]);
the first signal line is electrically connected to the second signal line (scan lines S1/S2, Para [0025]) through the first type of via hole (Para, [0078-0087]);
the signal line (Scan lines S3, S4, Para [ 0025]) for transmitting the power supply voltage signal (Para [ 0025], power supply line VSS) includes a third signal line and a fourth signal line, and the third signal line (Scan lines S3, S4, Para [ 0025]) is electrically connected to the fourth signal line through the second type of via hole (Para, [0078-0087]);
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine CAO first embodiment in light of CAO second embodiment teaching “the display panel includes a signal line (scan lines S1/S2, Para [ 0025]) for transmitting a reference voltage signal (Para [ 0025], power supply line, VDD ), and a signal line (Scan lines S3, S4, Para [ 0025]) for transmitting a power supply voltage signal (Para [ 0025], power supply line VSS);
the signal line (scan lines S1/S2, Para [0025]) for transmitting the reference voltage signal (Para [ 0025], power supply line, VDD ) includes a first signal line and a second signal line (scan lines S1/S2, Para [0025]);the first signal line is electrically connected to the second signal line (scan lines S1/S2, Para [0025]) through the first type of via hole (Para, [0078-0087]); the signal line (Scan lines S3, S4, Para [ 0025]) for transmitting the power supply voltage signal (Para [ 0025], power supply line VSS) includes a third signal line and a fourth signal line, and the third signal line (Scan lines S3, S4, Para [ 0025]) is electrically connected to the fourth signal line through the second type of via hole (Para, [0078-0087])” for further advantage such as performance of the display panel is improved.
Regarding claim 20. CAO discloses a display device comprising a display panel according to claim 1 (CAO, Para [0043]).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over CAO et al (US 2024/0268187 A1; hereafter CAO) as applied claims above and further in view of WU et al (US 2024/0023362 A1; hereafter WU).
Regarding claim 19. CAO discloses the display panel according to claim 1, BUT CAO fails to disclose wherein a thickness of the planarization layer is greater than a first thickness threshold, and the first thickness threshold is greater than or equal to 2.8 µm and less than or equal to 3.2 µm.
In a similar field of endeavor, WU discloses wherein a thickness of the planarization layer is greater than a first thickness threshold, and the first thickness threshold is greater than or equal to 2.8 µm and less than or equal to 3.2 µm (Para [0075]). In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). "[A] prior art reference that discloses a range encompassing a somewhat narrower claimed range is sufficient to establish a prima facie case of obviousness." In re Peterson, 315 F.3d 1325, 1330, 65 USPQ2d 1379, 1382-83 (Fed. Cir. 2003). >See also In re Harris, 409 F.3d 1339, 74 USPQ2d 1951 (Fed. Cir. 2005).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine CAO in light of WU teaching “wherein a thickness of the planarization layer is greater than a first thickness threshold, and the first thickness threshold is greater than or equal to 2.8 µm and less than or equal to 3.2 µm (Para [0075])” for further advantage such as to provide desire thickness and excellent light extraction efficiency.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOIN M RAHMAN whose telephone number is (571)272-5002. The examiner can normally be reached 8:30-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOIN M RAHMAN/Primary Examiner, Art Unit 2898
