DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
RESPONSE TO ARGUMENTS
Applicant’s arguments with respect to claims 1-6, 8-10 and 13-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
I. REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 8-10 and 13-20 are rejected under 35 U.S.C. 103 as being unpatentable over KEELY et al. (US Pub.: 2023/0195664) in view of AGARWAL et al. (US Pub.: 2022/0051985) and Yu et al. (US Pub.: 2021/0151408).
As per claim 1, KEELY teaches/suggests an integrated circuit, comprising: a first die (e.g. Fig. 3, ref. 304A: [0020]; [0025]); and a second die (e.g. Fig. 3, ref. 304B: [0020]; [0025]) connected to the first die via interface forming structure with the first die (Fig. 3; [0020]; [0025]; and [0035]-[0037]), connecting the first die with the second die for streaming data between the first die and the second die (Fig. 3; [0020]; and [0025]-[0038]); and one or more third dies (e.g. Fig. 3, ref. 304C: [0020]; [0025]); wherein the first die, the second die and the one or more third dies are connected (Fig. 3; [0020]; and [0025]-[0038]).
KEELY does not teach the integrated circuit, comprising: connect via a die-to-die (D2D) interface circuit in a D2D configuration forming a D2D structure; dies are connected in a torus configuration.
AGARWAL teaches/suggests an integrated circuit, comprising: connect via a die-to-die (D2D) interface circuit (e.g. associated with interconnect dies (130, 140, 150) in Fig. 1: [0021]) in a D2D configuration forming a D2D structure (Fig. 1; [0013]-[0016]; [0020]-[0022]; [0026]; [0030]; and [0045]-[0047]).
Yu teaches/suggests an integrated circuit, comprising: dies are connected in a torus configuration ([0061]).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include AGARWAL’s interconnect dies and Yu ‘s three-dimensional die network into KEELY’s circuitry for the benefit of implementing ultra-high density I/O connections so that dies integrated in a heterogenous fashion can act similar or better than a monolithic device (AGARWAL, [0016]) and improving speed, bandwidth and latency of data accessing (Yu, [0061]) to obtain the invention as specified in claim 1.
As per claim 2, KEELY, AGARWAL and Yu teach/suggest all the claimed features of claim 1 above, where KEELY, AGARWAL and Yu further teach/suggest the integrated circuit comprising wherein the D2D interface circuit comprises a plurality of bidirectional interface slices, and a pair of the bidirectional interface slices is connected to a corresponding superlane of a plurality of superlanes of the second die (KEELY, Fig. 3; [0020]; [0025]-[0038]; AGARWAL, Fig. 1; [0013]-[0016]; [0020]-[0022]; [0026]; [0030]; [0045]-[0047]; and Yu, [0061]), wherein it would have been obvious that the resulting combination further teach/suggests the above claimed features as data is communicated across the interconnect dies/D2D interface circuit properly.
As per claim 3, KEELY, AGARWAL and Yu teach/suggest all the claimed features of claim 1 above, where KEELY, AGARWAL and Yu further teach/suggest the integrated circuit comprising wherein the D2D interface circuit comprises a D2D core interface circuit connected to a corresponding subset of a plurality of superlanes of the first die (KEELY, Fig. 3; [0020]; [0025]-[0038]; AGARWAL, Fig. 1; [0013]-[0016]; [0020]-[0022]; [0026]; [0030]; [0045]-[0047]; and Yu, [0061]).
As per claim 4, KEELY, AGARWAL and Yu teach/suggest all the claimed features of claim 1 above, where KEELY, AGARWAL and Yu further teach/suggest the integrated circuit comprising wherein the D2D interface circuit comprises a plurality of D2D interface banks, each of the plurality of D2D interface banks connecting a cluster of a first plurality of superlanes of the first die to a cluster of a second plurality of superlanes of the second die (KEELY, Fig. 3; [0020]; [0025]-[0038]; AGARWAL, Fig. 1; [0013]-[0016]; [0020]-[0022]; [0026]; [0030]; [0045]-[0047]; and Yu, [0061]), wherein it would have been obvious that the resulting combination further teach/suggests the above claimed features as data is communicated across the interconnect dies/D2D interface circuit properly.
As per claim 5, KEELY, AGARWAL and Yu teach/suggest all the claimed features of claim 4 above, where KEELY, AGARWAL and Yu further teach/suggest the integrated circuit comprising wherein a size of each of the plurality of D2D interface banks along a first direction matches a size of the cluster of the second plurality of superlanes along the first direction (KEELY, Fig. 3; [0020]; [0025]-[0038]; AGARWAL, Fig. 1; [0013]-[0016]; [0020]-[0022]; [0026]; [0030]; [0045]-[0047]; and Yu, [0061]), wherein it would have been obvious that the resulting combination further teach/suggests the above claimed features as data is communicated across the interconnect dies/D2D interface circuit properly.
As per claim 6, KEELY, AGARWAL and Yu teach/suggest all the claimed features of claim 4 above, where KEELY, AGARWAL and Yu further teach/suggest the integrated circuit comprising wherein each of the plurality of D2D interface banks comprises a plurality of D2D interface macros, and each of the plurality of D2D interface macros comprises a respective bidirectional interface slice of a plurality of bidirectional interface slices (KEELY, Fig. 3; [0020]; [0025]-[0038]; AGARWAL, Fig. 1; [0013]-[0016]; [0020]-[0022]; [0026]; [0030]; [0045]-[0047]; and Yu, [0061]), wherein it would have been obvious that the resulting combination further teach/suggests the above claimed features as data is communicated across the interconnect dies/D2D interface circuit properly.
As per claim 8, KEELY, AGARWAL and Yu teach/suggest all the claimed features of claim 1 above, where KEELY, AGARWAL and Yu further teach/suggest the integrated circuit comprising wherein the first die, the second die, and the one or more third dies are configured to function as a single core processor for model-parallelism across the first die, the second die, and the one or more third dies (KEELY, Fig. 3; [0015]; [0020]; [0025]-[0038]; [0044]; [0054]; AGARWAL, Fig. 1; [0013]-[0016]; [0020]-[0022]; [0026]; [0030]; [0045]-[0047]; and Yu, [0061]), wherein it would have been obvious that the resulting combination further teach/suggests the above claimed features as data is communicated across the interconnect dies/D2D interface circuit properly.
As per claim 9, KEELY, AGARWAL and Yu teach/suggest all the claimed features of claim 1 above, where KEELY, AGARWAL and Yu further teach/suggest the integrated circuit comprising wherein the torus configuration comprises a first folded mesh structure coupled to a second folded mesh structure to form the torus configuration (KEELY, Fig. 3; [0015]; [0020]; [0025]-[0038]; [0044]; [0054]; AGARWAL, Fig. 1; [0013]-[0016]; [0020]-[0022]; [0026]; [0030]; [0045]-[0047]; and Yu, [0061]), wherein it would have been obvious that the resulting combination further teach/suggests the above claimed features as data is communicated across the interconnect dies/D2D interface circuit in the three-dimensional torus network/configuration.
As per claim 10, KEELY, AGARWAL and Yu teach/suggest all the claimed features of claim 9 above, where KEELY, AGARWAL and Yu further teach/suggest the integrated circuit comprising: wherein the one or more third dies comprise six third dies, wherein the first folded mesh structure comprises the first die, the second die, and two of the six third dies connected in a first folded mesh configuration, and wherein the second folded mesh structure comprises four of the six third dies connected in a second folded mesh configuration (KEELY, Fig. 3; [0015]; [0020]; [0025]-[0038]; [0044]; [0054]; AGARWAL, Fig. 1; [0013]-[0016]; [0020]-[0022]; [0026]; [0030]; [0045]-[0047]; and Yu, [0061]), wherein it would have been an obvious design choice to one of ordinary skilled in the art to further implement the above configuration for the three-dimensional torus network/configuration.
As per claim 13, KEELY, AGARWAL and Yu teach/suggest all the claimed features of claim 9 above, where KEELY, AGARWAL and Yu further teach/suggest the integrated circuit comprising wherein the first, second, and third dies connected in the first folded mesh structure are configured to operate as a single core processor for model-parallelism across the first folded mesh structure (KEELY, Fig. 3; [0015]; [0020]; [0025]-[0038]; [0044]; [0054]; AGARWAL, Fig. 1; [0013]-[0016]; [0020]-[0022]; [0026]; [0030]; [0045]-[0047]; and Yu, [0061]), wherein it would have been an obvious design choice to one of ordinary skilled in the art to further implement the above configuration for the three-dimensional torus network/configuration.
As per claim 14, KEELY, AGARWAL and Yu teach/suggest all the claimed features of claim 1 above, where KEELY, AGARWAL and Yu further teach/suggest the integrated circuit comprising wherein: the first die comprises a first tensor streaming processor (TSP) (e.g. wherein it would have been obvious to one of ordinary skilled in the art to further implement the TSP as artificial intelligent processor(s): [0015] of KEELY) having a first plurality of functional units connected at least in part via a first plurality of superlanes; and the second die comprises a second TSP having a second plurality of functional units connected at least in part via a second plurality of superlanes, a high-bandwidth memory, and the D2D interface circuit (KEELY, Fig. 3; [0015]; [0020]; [0025]-[0038]; [0044]; [0054]; AGARWAL, Fig. 1; [0013]-[0016]; [0020]-[0022]; [0026]; [0030]; [0045]-[0047]; and Yu, [0061]), wherein it would have been obvious that the resulting combination further teach/suggests the above claimed features as data is communicated across the interconnect dies/D2D interface circuit properly.
As per claim 15, KEELY, AGARWAL and Yu teach/suggest all the claimed features of claim 1 above, where KEELY, AGARWAL and Yu further teach/suggest the integrated circuit comprising wherein the second die is connected to the first die in a back-to-back (B2B) configuration or in a face-to-face (F2F) configuration forming the D2D structure (KEELY, Fig. 3; [0020]; [0025]-[0038]; AGARWAL, Fig. 1; [0013]-[0016]; [0020]-[0022]; [0026]; [0030]; [0045]-[0047]; and Yu, [0061]), wherein it would have been obvious that the resulting combination further teach/suggests the above claimed features.
As per claim 16, KEELY teaches/suggests a method comprising: initiating, by a compiler (e.g. it is obvious and/or well-known to one of ordinary skilled in the art for a computer system to have compiler to properly provide the instruction to be executed by the processing unit(s)), issuance of a plurality of instructions for execution by a plurality of processing units across a first die (e.g. Fig. 3, ref. 304A: [0020]; [0025]) and a second die (e.g. Fig. 3, ref. 304B: [0020]; [0025]), the second die connected to the first die via interface forming a structure with the first die (Fig. 3; [0020]; [0025]; and [0035]-[0037]), wherein the first die, the second die and one or more third dies (e.g. Fig. 3, ref. 304C: [0020]; [0025]) are connected (Fig. 3; [0020]; and [0025]-[0038]);and
initiating, by the compiler, streaming of data between the first die and the second die via the interface (Fig. 3; [0020]; and [0025]-[0038]).
KEELY does not teach the method comprising:
connect via a die-to-die (D2D) interface circuit in a D2D configuration forming a D2D structure, wherein dies are connected in a torus configuration; and
operating with a first plurality of data paths of first and a second plurality of data paths of second via the D2D interface circuit.
AGARWAL teaches/suggests a method comprising: connect via a die-to-die (D2D) interface circuit (e.g. associated with interconnect dies (130, 140, 150) in Fig. 1: [0021]) in a D2D configuration forming a D2D structure; and operating with a first plurality of data paths of first and a second plurality of data paths of second via the D2D interface circuit (e.g. associated with interconnect die providing I/O connections/data paths between dies: [0016]; [0021]-[0022]) (Fig. 1; [0013]-[0016]; [0020]-[0022]; [0026]; [0030]; and [0045]-[0047).
Yu teaches/suggests a method comprising: dies are connected in a torus configuration ([0061]).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include AGARWAL’s interconnect dies and Yu ‘s three-dimensional die network into KEELY’s circuitry for the benefit of implementing ultra-high density I/O connections so that dies integrated in a heterogenous fashion can act similar or better than a monolithic device (AGARWAL, [0016]) and improving speed, bandwidth and latency of data accessing (Yu, [0061]) to obtain the invention as specified in claim 16.
As per claim 17, KEELY, AGARWAL and Yu teach/suggest all the claimed features of claim 16 above, where KEELY, AGARWAL and Yu further teach/suggest the method further comprising: initiating, by the compiler, streaming of data across the first die, second die, and the one or more third dies (KEELY, Fig. 3; [0015]; [0020]; [0025]-[0038]; [0044]; [0054]; AGARWAL, Fig. 1; [0013]-[0016]; [0020]-[0022]; [0026]; [0030]; [0045]-[0047]; and Yu, [0061])
As per claim 18, KEELY, AGARWAL and Yu teach/suggest all the claimed features of claim 17 above, where KEELY, AGARWAL and Yu further teach/suggest the method further comprising: configuring, by the compiler, the first die, second die, and the one or more third dies to function as a single core processor for model-parallelism across the first die, second die, and the one or more third dies (KEELY, Fig. 3; [0015]; [0020]; [0025]-[0038]; [0044]; [0054]; AGARWAL, Fig. 1; [0013]-[0016]; [0020]-[0022]; [0026]; [0030]; [0045]-[0047]; and Yu, [0061]), wherein it would have been obvious that the resulting combination further teach/suggests the above claimed features as data is communicated across the interconnect dies/D2D interface circuit properly.
As per claim 19, KEELY teaches/suggests a non-transitory computer-readable storage medium comprising stored thereon computer executable instructions, which when executed by a compiler operating on at least one computer processor cause the at least one computer processor to: initiate issuance of a plurality of instructions for execution by a plurality of processing units across a first die (e.g. Fig. 3, ref. 304A: [0020]; [0025]) and a second die (e.g. Fig. 3, ref. 304B: [0020]; [0025]), the second die connected to the first die via interface forming a structure with the first die (Fig. 3; [0020]; [0025]; and [0035]-[0037]), wherein the first die, the second die and one or more third dies (e.g. Fig. 3, ref. 304C: [0020]; [0025]) are connected (Fig. 3; [0020]; and [0025]-[0038]); and initiate streaming of data between the first die and the second die via the interface (Fig. 3; [0020]; and [0025]-[0038]).
KEELY does not teach causing the at least one processor to:
connect via a die-to-die (D2D) interface circuit in a D2D configuration forming a D2D structure, wherein dies are connected in a torus configuration; and
operating with a first plurality of data paths of first and a second plurality of data paths of second via the D2D interface circuit.
AGARWAL teaches/suggests a system comprising: connect via a die-to-die (D2D) interface circuit (e.g. associated with interconnect dies (130, 140, 150) in Fig. 1: [0021]) in a D2D configuration forming a D2D structure; and operating with a first plurality of data paths of first and a second plurality of data paths of second via the D2D interface circuit (e.g. associated with interconnect die providing I/O connections/data paths between dies: [0016]; [0021]-[0022]) (Fig. 1; [0013]-[0016]; [0020]-[0022]; [0026]; [0030]; and [0045]-[0047).
Yu teaches/suggests a system comprising: dies are connected in a torus configuration ([0061]).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include AGARWAL’s interconnect dies and Yu ‘s three-dimensional die network into KEELY’s circuitry for the benefit of implementing ultra-high density I/O connections so that dies integrated in a heterogenous fashion can act similar or better than a monolithic device (AGARWAL, [0016]) and improving speed, bandwidth and latency of data accessing (Yu, [0061]) to obtain the invention as specified in claim 19.
As per claim 20, KEELY, AGARWAL and Yu teach/suggest all the claimed features of claim 19 above, where KEELY, AGARWAL and Yu further teach/suggest the non-transitory computer-readable storage medium comprising: wherein the instructions further cause the computer processor to: initiate streaming of data across the first die, second die, and the one or more third dies; and configure the first die, second die, and the one or more third dies to function as a single core processor for model-parallelism across the first die, second die, and the one or more third dies of the D2D structure (KEELY, Fig. 3; [0015]; [0020]; [0025]-[0038]; [0044]; [0054]; AGARWAL, Fig. 1; [0013]-[0016]; [0020]-[0022]; [0026]; [0030]; [0045]-[0047]; and Yu, [0061]), wherein it would have been obvious that the resulting combination further teach/suggests the above claimed features as data is communicated across the interconnect dies/D2D interface circuit properly.
II. CLOSING COMMENTS
CONCLUSION
STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. 707.07(i):
CLAIMS REJECTED IN THE APPLICATION
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHUN KUAN LEE whose telephone number is (571)272-0671. The examiner can normally be reached Monday-Friday.
IMPORTANT NOTE
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye can be reached on (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CHUN KUAN LEE/Primary Examiner
Art Unit 2181 March 10, 2026