Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
In response to the Communications dated August 22, 2024, claims 1-4, 7, 9, 10, 12-17, 19-21, 26
and 32-34 are active in this application.
Specification
If there are cross-reference to related applications, please include the
respective patent numbers, if known.
Information Disclosure Statement
The information disclosure statements filed August 22, 2024 through September 10, 2025 have
been considered.
Claim Objections
Claims 2, 3, 7, 9, 10, 13-15, 17, 20, 21, 26, and 33 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 12, 16 and 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mukhamov et al. [US Patent # 9,627,045].
With respect to claim 1, Mukhamov et al. disclose a write circuit for writing state into a plurality of superconducting memory cells, the write circuit comprising: a control circuit [“pulse circuit coupled to the electrical contact" designed to generate a series of single flux quantum (SFQ) pulses to switch the memory cell between states. Additionally, Mukhamov et al. indicate that there exists a “write port” that uses a “magnetic thin film transformer” (or a conductive write line) that can be controlled by external circuits to inject spin-polarized electrons or magnetic fields – col. 5, lines 50-65 and fig. 4; and, col. 6, lines 1-15 and fig. 5]; a first plurality of write lines, each of the first plurality of write lines being configured to convey a first write current [Mukhamov et al. indicate the use of “X and Y-directional write lines” that carry current to generate magnetic fields to switch the magnetization of the MJJ – col. 4, lines 10-30 and fig. 3]; and a first plurality of non-superconducting switch circuits [The memory array is accessed via selected X and Y-directional write lines that can switch the MJJ's magnetization (Column 8, lines 39-50)], each of the first plurality of non-superconducting switch circuits [The write port connects to the ferromagnetic material, and a pulse circuit generates single flux quantum pulses to switch the cell's states (Column 8, lines 55-60)] being integrated with a corresponding one of the first plurality of write lines and being configured to receive at least a first control signal supplied by the control circuit for enabling the first write current to flow through the corresponding one of the first plurality of write lines into at least a selected one of the plurality of superconducting memory cells associated with the corresponding one of the first plurality of write lines [“The write port comprises an electrical contact in communication with the ferromagnetic material, further comprising a pulse circuit coupled to the electrical contact configured to generate a series of single flux quantum pulses which cause the Josephson junction memory cell to switch between states." – col. 6, lines 18-36].
With respect to claim 12, Mukhamov et al. disclose a plurality of coupling elements, each of the coupling elements being connected in series with a given one of the first plurality of non-superconducting switch circuits in a corresponding one of the first plurality of write lines. It is noted that the coupling elements are being interpreted as being nodes (which are inherent to inputs/outputs terminals).
With respect to claim 16, Mukhamov et al. disclose each of at least a subset of the plurality of superconducting memory cells comprises a magnetic Josephson junction. See last paragraph of col. 2.
With respect to claim 19, Mukhamov et al. disclose the write circuit is configurable for writing state into a single one of the plurality of superconducting memory cells at a given time [“…with X and Y write line selection each memory cell is individually selectable during a write cycle.” – col. 7, lines 10-15].
Allowable Subject Matter
Claims 32 and 34 are allowable over the prior art of record.
The following is an Examiner's statement of reasons for the indication of
allowable subject matter: the prior art of records does not show (in addition to the other
elements in the claim) the following:
-with respect to claim 2: The write circuit according to claim 1, further comprising: a second plurality of write lines, each of the second plurality of write lines being configured to convey a second write current; and a second plurality of non-superconducting switch circuits, each of the second plurality of non-superconducting switch circuits being integrated with a corresponding one of the second plurality of write lines and being configured to receive at least a second control signal supplied by the control circuit for enabling the second write current to flow through the corresponding one of the second plurality of write lines.
-with respect to claim 3: The write circuit according to claim 1, further comprising at least first and second interconnections, a first end of each of the first plurality of write lines being operably connected to the first interconnection, a second end of each of the first plurality of write lines being operably connected to a first terminal of a corresponding one of the first plurality of non-superconducting switch circuits, and a second terminal of the corresponding one of the first plurality of non-superconducting switch circuits being operably connected to the second interconnection, wherein the first and second interconnections are operably connected to first and second terminals, respectively, of at least a first current source configured to supply the first write current.
-with respect to claim 7: The write circuit according to claim 1, wherein each of at least a subset of the first plurality of write lines is configured to pass over and/or under each of a corresponding one of the superconducting memory cells at a prescribed angle relative to a major axis of a magnetic Josephson junction of the memory cell.
-with respect to claim 13: The write circuit according to claim 12, wherein each of at least a subset of the plurality of coupling elements comprises a transformer including a primary wire, connected in series with the given one of the first plurality of non-superconducting switch circuits, and a secondary wire configured to pass through or in close proximity to a corresponding one of the superconducting memory cells.
-with respect to claim 15: The write circuit according to claim 1, wherein the control circuit comprises a shift register including an input port configured to receive an input data pattern to be applied to the shift register for controlling a write operation of the superconducting memory cells, wherein control signals for activating the first plurality of non- superconducting switch circuits are generated at respective outputs of the shift register.
-with respect to claim 17: The write circuit according to claim 1, wherein at least a given one of the first plurality of write lines is coupled to a true magnetic Josephson junction (MJJ) memory cell and a complement MJJ memory cell associated therewith, the true and complement MJJ memory cells being included in the plurality of superconducting memory cells, the given one of the first plurality of write lines being configured to convey the first write current across the true MJJ memory cell in a first direction and to convey the first write current across the complement MJJ memory cell in a second direction opposite the first direction.
-with respect to claim 26: The write circuit according to claim 1, wherein the write circuit comprises: at least one first write circuit connected to the first plurality of write lines, the first write circuit including at least one superconducting switch circuit configured to selectively apply the first write current to at least a given one of the first plurality of write lines for writing state into one or more corresponding memory cells of the plurality of superconducting memory cells associated with the given one of the first plurality of write lines in response to the first control signal; and at least one second write circuit connected to a second plurality of write lines, each of the second plurality of write lines being configured to convey a second write line current, the second write circuit including at least one non-superconducting switch circuit configured to selectively apply the second write current to at least a given one of the second plurality of write lines for selecting one or more corresponding memory cells of the plurality of superconducting memory cells associated with the given one of the second plurality of write lines in response to at least a second control signal.
-with respect to claim 32, a conversion circuit, the conversion circuit being configured to receive a superconducting encoded write address and/or a superconducting data signal, and to generate the first and/or second non-superconducting control signals as a function of the superconducting encoded write address, receive a superconducting data signal and to generate the at least second non-superconducting control signal as a function of and/or the superconducting data signal.
-with respect to claim 33: The write circuit according to claim 1, further comprising one or more superconducting loops, each of the one or more superconducting loops comprising: a Josephson junction; an inductor; and a superconducting memory cell of the plurality of superconducting memory cells, the superconducting memory cell, the inductor and the Josephson junction being connected together in series to form the superconducting loop.
-with respect to claim 34, transferring the state of the one or more memory cells of the plurality of superconducting memory cells read from the selected at least one memory circuit to an evaluation circuit; verifying that the stored state of the one or more memory cells read from the selected at least one memory circuit is the same as the prescribed logic state intended to be written into the one or more memory cells.
Conclusion
For applicant’s benefit portions of the cited reference(s) have been cited to aid in
the review of the rejection(s). While every attempt has been made to be thorough and consistent within the rejection it is noted that the PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS. See MPEP 2141.02 VI.
When responding to the Office action, Applicants are advised to provide
the Examiner with line and page numbers of the application and/or references cited to assist the Examiner in the prosecution of this case.
Any inquiry concerning this communication or earlier communications
from the Examiner should be directed to Michael T. Tran whose telephone number is (571) 272-1795. Interview agendas may be emailed to Michael.tran@uspto.gov. The Examiner can normally be reached on Monday-Thursday from 6:00AM-4:30 P.M.
Any inquiry of a general nature or relating to the status of this application.
should be directed to the Group receptionist whose telephone number is (571) 272-1650.
/MICHAEL T TRAN/Primary Examiner, Art Unit 2827 January 28, 2026