DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “A semiconductor element” twice. It is unclear whether the second recited “A semiconductor element” (line 2) is intended to relate back to “A semiconductor element” (line 1) or to set forth an additional semiconductor element.
Claim 1 recites limitation “the SiO2 layer” (line 11) that lacks antecedent basis in the claim.
Claim 2 recites “a SiO2 layer” and claim 1 recites “the SiO2 layer” (line 11). It is unclear whether the second recited “a SiO2 layer” of claim 2 is intended to relate back to “the SiO2 layer” of claim 1 or to set forth an additional SiO2 layer.
Claim 7 recites “a SiO2 layer” and claim 1 recites “the SiO2 layer” (line 3). It is unclear whether the second recited “a SiO2 layer” of claim 7 is intended to relate back to “the SiO2 layer” of claim 1 or to set forth an additional SiO2 layer.
Claim 7 (claim 8) recites “a first SiO2 layer” and “a second SiO2 layer”, However, claim 1 also recites “a first SiO2 layer” and “a second SiO2 layer”. It is unclear whether the second recited “a first SiO2 layer” and “a second SiO2 layer” of claim 7 (claim 8) are intended to relate back to “a first SiO2 layer” and “a second SiO2 layer” of claim 1 or to set forth additional first SiO2 layer and second SiO2 layer.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9 are rejected under 35 U.S.C. 103 as being unpatentable over US 2013/0328120 to Ueno et al. (hereinafter Ueno) in view of Furukawa et al. (US 2019/0260178, hereinafter Furukawa) and Uemura et al. (US 2013/0278855, hereinafter Uemura).
Claim 1 recites a semiconductor element (e.g., a vertical semiconductor device of Group III nitride semiconductor including a diode) (Ueno, Figs. 1, 4, ¶0002, ¶0010-¶0019, ¶0042-¶0072, ¶0083-¶0084) comprising:
A semiconductor element (e.g., a diode) (Ueno, Fig. 1, ¶0042-¶0072) comprising:
a semiconductor layer (e.g., n-GaN) comprising at least one MESA structure (e.g., steps 15 form mesa) (Ueno, Fig. 1, ¶0044-¶0048);
a field plate (17) (Ueno, Fig. 1, ¶0052-¶0054) disposed covering at least a part of the semiconductor layer (11); and
an insulating film (16) (Ueno, Fig. 1, ¶0049-¶0052) located between the semiconductor layer (11) and the field plate (17),
wherein the semiconductor layer (11) (Ueno, Fig. 1, ¶0042-¶0045) is an n- type gallium nitride layer (n-GaN), and
a thickness (e.g., at the bottom surface 15b of the step 15) of a bottom portion of the insulating film (16) (Ueno, Figs. 1, 4, ¶0050-¶0051) covering a bottom portion (15b) of a groove portion of the semiconductor layer (11) is greater (Ueno, Fig. 4, ¶0051) than a thickness of a side wall portion (e.g., at the side surface 15a of the step 15) of the insulating film (16) covering a side wall portion (15a) of the groove portion of the semiconductor layer (11), and
the SiO2 layer (e.g., the insulating film includes a plurality of layers, for example Al2O3/SiO2 or SiO2/Al2O3) (Ueno, Fig. 1, ¶0050) comprises a first SiO2 layer.
Further, Ueno does not specifically disclose a first SiO2 layer having a density of 1.9 g/cm3 or more and 2.1 g/cm3 or less and a second SiO2 layer having a density of more than 2.1 g/cm3 and 2.3 g/cm3 or less.
However, Ueno teaches forming a passivation layer as the insulating film including a plurality of layers, to achieve a desired breakdown voltage (Ueno, Fig. 1, ¶0051).
Further, Furukawa teaches forming a passivation layer (Furukawa, Fig. 18, ¶0033-¶0034, ¶0040-¶0042, ¶0064-¶0065, ¶0068) for a semiconductor element including n-GaN layer (112), wherein the passivation layer includes a plurality of silicon oxide films (e.g., 132/134 and 232/234) having high density and low denisty, to protect the semiconductor element from moisture and metal ions (Furukawa, ¶0064-¶0065).
Further, Uemura teaches forming a protective film (Uemura, Figs. 4-5, ¶0048-¶0051, ¶0060-¶0077) having a plurality thin film layers of different densities by a plasma CVD method and including a first silicon oxide layer having a lower film density of 1.89 g/cm3 and a second silicon oxide layer having a higher film density of 2.21 g/cm3 such that a difference between the lower density silicon oxide layer and the higher density silicon oxide layer is 0.3 g/cm3 or more, to improve passivation performance, to alleviate stress in the passivation layer, and to prevent peeling from the semiconductor structure (Uemura, ¶0048-¶0051, ¶0061, ¶0063, ¶0069, ¶0075-¶0076). In Uemura, the film formation conditions are optimized depending on a film formation device to provide a plurality thin film silicon oxide layers of different densities (Uemura, ¶0048-¶0051).
Thus, Uemura recognizes that film formation conditions to form silicon oxide layers having different densities impact passivation performance of the protective film including the silicon oxide layers of different densities. Further, Furukawa recognizes that the protective film including the silicon oxide layers of different densities impacts passivation performance of the protective film. Thus, film formation conditions to form silicon oxide layers having different densities are result-effective variables.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, film formation conditions to form silicon oxide layers having different densities as Uemura and Furukawa have identified film formation conditions to form silicon oxide layers having different densities as result-effective variables. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at film formation conditions to form silicon oxide layers having different densities having a specific density difference between the lower density silicon oxide layer and the higher density silicon oxide layer such that a first SiO2 layer having a density of 1.9 g/cm3 or more and 2.1 g/cm3 or less and a second SiO2 layer having a density of more than 2.1 g/cm3 and 2.3 g/cm3 or less, in order to improve passivation performance, to alleviate stress in the passivation layer, and to prevent peeling from the semiconductor structure as taught by Uemura (¶0048-¶0051, ¶0061, ¶0063, ¶0069, ¶0075-¶0076) and Furukawa (¶0064-¶0065) (MPEP 2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor element of Ueno by forming a passivation layer including a plurality of silicon oxide (SiO2) layers, and optimizing film formation conditions of forming the first SiO2 layer and the second SiO2 layer having different densities as taught by Uemura and Furukawa, wherein the first SiO2 layer and the second SiO2 layer have a specific density difference between the lower density silicon oxide layer and the higher density silicon oxide layer as taught by Uemura to have first SiO2 layer having a density of 1.9 g/cm3 or more and 2.1 g/cm3 or less and a second SiO2 layer having a density of more than 2.1 g/cm3 and 2.3 g/cm3 or less, in order to improve passivation performance, to alleviate stress in the passivation layer, and to prevent peeling from the semiconductor structure; and to protect the semiconductor element from moisture and metal ions (Uemura, ¶0048-¶0051, ¶0061, ¶0063, ¶0069, ¶0075-¶0076; Furukawa, ¶0064-¶0065).
Regarding claim 2, Ueno in view of Furukawa and Uemura discloses the semiconductor element according to claim 1. Further, Ueno discloses the semiconductor element, wherein the insulating film (16) comprises a SiO2 layer (e.g., Al2O3/SiO2 or SiO2/Al2O3) (Ueno, Fig. 1, ¶0050).
Regarding claim 3, Ueno in view of Furukawa and Uemura discloses the semiconductor element according to claim 2. Further, Ueno discloses the semiconductor element, wherein the insulating film (16) further comprises an Al2O3 layer (e.g., Al2O3/SiO2 or SiO2/Al2O3) (Ueno, Fig. 1, ¶0050).
Regarding claim 5, Ueno in view of Furukawa and Uemura discloses the semiconductor element according to claim 1. Further, Ueno does not specifically disclose that the thickness of the bottom portion of the insulating film is 1.5 times or more and 5 times or less the thickness of the side wall portion of the insulating film.
However, Ueno teaches that the smaller the thickness of the protective film (16) (Ueno, Fig. 1, ¶0051, ¶0055-¶0063, ¶0065) at the side surface (15a) is, the higher the breakdown voltage, and the larger thickness of the protective film (16) at the bottom surface (15b) would reduce the concentration of the electric field at an end portion of the field plate electrode (17) formed via the protective film (16) on the bottom surface (15b). Therefore, the protective film (16) is preferably formed so as to have a smaller thickness (d) at the side surface (15a) than the thickness (d0) at the bottom surface (15b). Also, the dielectric constant of the whole protective film is adjusted by forming the protective film comprising a plurality of layers, thereby facilitating the design to achieve a desired breakdown voltage (Ueno, Fig. 1, ¶0051). The distance from the surface (16a) (Ueno, Fig. 1, ¶0055-¶0063) of the protection layer (16) to the top of the semiconductor layer (12) is defined as h (mm), the thickness of the protection layer (16) at the side surface (15a) is defined as d (mm), and 0.5≤h/d≤3. The thickness of the protection layer (16) at the bottom surface (15b) is defined as d0 (mm), and the distance from the bottom (15b) of the step and the top of the semiconductor layer (12) is defined as the height h0 of the mesa.
Thus, a person of ordinary skill in the art would recognize that with the thickness of the protection layer d=800nm (Ueno, Fig. 1, ¶0065), h=3*d=2400nm (2.4 mm), and with the height of mesa h0 of about 5 mm, the thickness of the protection layer d0=h0-h=5mm-2.4 mm=2.6 mm. Therefore, the thickness d0 of the bottom portion of the insulating film (16) would be about 3 times the thickness d of the side wall portion of the insulating film (16).
Thus, Ueno recognizes that the height of the mesa, the thickness of the protection layer at the side surface and the bottom surface, and the dielectric constant of the whole protective film comprising a plurality of layers impact the breakdown voltage and the concentration of the electric field at an end portion of the field plate electrode. Thus, the height of the mesa, the thickness of the protection layer at the side surface and the bottom surface, and the dielectric constant of the whole protective film comprising a plurality of layers are result-effective variables.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, the height of the mesa, the thickness of the protection layer at the side surface and the bottom surface, and the dielectric constant of the whole protective film comprising a plurality of layers as Ueno has identified the height of the mesa, the thickness of the protection layer at the side surface and the bottom surface, and the dielectric constant of the whole protective film as result-effective variables. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at specific height of the mesa, the thickness of the protection layer at the side surface and the bottom surface, and the dielectric constant of the whole protective film, such that the thickness of the bottom portion of the insulating film is 1.5 times or more and 5 times or less the thickness of the side wall portion of the insulating film, in order to provide higher the breakdown voltage and reduced concentration of the electric field at an end portion of the field plate electrode as taught by Ueno (¶0051, ¶0055-¶0063, ¶0065, ¶0071-¶0072) (MPEP 2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor element of Ueno by optimizing the height of the mesa, the thickness of the protection layer at the side surface and the bottom surface, and the dielectric constant of the whole protective film as taught by Ueno to have the semiconductor element, wherein the thickness of the bottom portion of the insulating film is 1.5 times or more and 5 times or less the thickness of the side wall portion of the insulating film, in order to improve breakdown voltage performance and to reduce the concentration of the electric field of the vertical semiconductor device with a field plate electrode (Ueno, ¶0010, ¶0051, ¶0055-¶0063, ¶0065, ¶0071-¶0072).
Regarding claim 6, Ueno in view of Furukawa and Uemura discloses the semiconductor element according to claim 1. Further, Ueno discloses a semiconductor device (e.g., a vertical semiconductor device of Group III nitride semiconductor including a diode) (Ueno, Figs. 1, 4, ¶0002, ¶0010-¶0019, ¶0042-¶0072, ¶0083-¶0084) comprising: the semiconductor element according to claim 1.
Regarding claims 7 and 8, Ueno in view of Furukawa and Uemura discloses a manufacturing method for the semiconductor element according to claim 1, wherein the insulating film comprises a SiO2 layer (e.g., the insulating film includes a plurality of layers, for example Al2O3/SiO2 or SiO2/Al2O3) (Ueno, Fig. 1, ¶0050).
Further, Ueno does not specifically disclose that the SiO2 layer is formed by vaporizing or plasma CVD, and the SiO2 layer comprises a first SiO2 layer having a density of 1.9 g/cm3 or more and 2.1 g/cm3 or less and a second SiO2 layer having a density of more than 2.1 g/cm3 and 2.3 g/cm3 or less (as claimed in claim 7); wherein the insulating film comprises a first SiO2 layer and a second SiO2 layer, and the first SiO2 layer is formed by vaporizing, and the second SiO2 layer is formed by plasma CVD (as claimed in claim 8).
However, Furukawa teaches forming a passivation layer (Furukawa, Fig. 18, ¶0033-¶0034, ¶0040-¶0042, ¶0064-¶0065, ¶0068) for a semiconductor element including n-GaN layer (112), wherein the passivation layer includes a plurality of silicon oxide films (e.g., 132/134 and 232/234) having high density and low denisty, to protect the semiconductor element from moisture and metal ions (Furukawa, ¶0064-¶0065).
Further, Uemura teaches forming a protective film (Uemura, Figs. 4-5, ¶0043, ¶0048-¶0051, ¶0060-¶0077) having a plurality thin film layers of different densities by a plasma chemical vapor deposition (CVD) method (Uemura, Figs. 4-5, ¶0043), and including a first silicon oxide layer having a lower film density of 1.89 g/cm3 and a second silicon oxide layer having a higher film density of 2.21 g/cm3 such that a difference between the lower density silicon oxide layer and the higher density silicon oxide layer is 0.3 g/cm3 or more, to improve passivation performance, to alleviate stress in the passivation layer, and to prevent peeling from the semiconductor structure (Uemura, ¶0048-¶0051, ¶0061, ¶0063, ¶0069, ¶0075-¶0076). In Uemura, the film formation conditions are optimized depending on a film formation device to provide a plurality thin film silicon oxide layers of different densities (Uemura, ¶0048-¶0051).
Note that limitation of claim 8 “vaporizing” is interpreted as a broad limitation that incudes chemical vapor deposition (CVD) method. Further, specification does not provide any description of “vaporizing” method of the first SiO2 layer.
Thus, Uemura recognizes that film formation conditions to form silicon oxide layers having different densities impact passivation performance of the protective film including the silicon oxide layers of different densities. Further, Furukawa recognizes that the protective film including the silicon oxide layers of different densities impacts passivation performance of the protective film. Thus, film formation conditions to form silicon oxide layers having different densities are result-effective variables.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, film formation conditions to form silicon oxide layers having different densities as Uemura and Furukawa have identified film formation conditions to form silicon oxide layers having different densities as result-effective variables. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at film formation conditions to form silicon oxide layers having different densities having a specific density difference between the lower density silicon oxide layer and the higher density silicon oxide layer such that a first SiO2 layer having a density of 1.9 g/cm3 or more and 2.1 g/cm3 or less and a second SiO2 layer having a density of more than 2.1 g/cm3 and 2.3 g/cm3 or less, in order to improve passivation performance, to alleviate stress in the passivation layer, and to prevent peeling from the semiconductor structure as taught by Uemura (¶0048-¶0051, ¶0061, ¶0063, ¶0069, ¶0075-¶0076) and Furukawa (¶0064-¶0065) (MPEP 2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the manufacturing method for the semiconductor element of Ueno by forming a passivation layer including a plurality of silicon oxide (SiO2) layers, and optimizing film formation conditions of forming the first SiO2 layer and the second SiO2 layer having different densities as taught by Uemura and Furukawa, wherein the first SiO2 layer and the second SiO2 layer have a specific density difference between the lower density silicon oxide layer and the higher density silicon oxide layer as taught by Uemura to have the manufacturing method for the semiconductor element, wherein the SiO2 layer is formed by vaporizing or plasma CVD, and the SiO2 layer comprises a first SiO2 layer having a density of 1.9 g/cm3 or more and 2.1 g/cm3 or less and a second SiO2 layer having a density of more than 2.1 g/cm3 and 2.3 g/cm3 or less (as claimed in claim 7); wherein the insulating film comprises a first SiO2 layer and a second SiO2 layer, and the first SiO2 layer is formed by vaporizing, and the second SiO2 layer is formed by plasma CVD (as claimed in claim 8), in order to improve passivation performance, to alleviate stress in the passivation layer, and to prevent peeling from the semiconductor structure; and to protect the semiconductor element from moisture and metal ions (Uemura, ¶0043, ¶0048-¶0051, ¶0061, ¶0063, ¶0069, ¶0075-¶0076; Furukawa, ¶0064-¶0065).
Regarding claim 9, Ueno in view of Furukawa and Uemura discloses the manufacturing method for the semiconductor element, according to claim 8. Further, Ueno does not specifically disclose that the insulating film comprises the first SiO2 layer and the second SiO2 layer in order from the semiconductor layer.
However, Furukawa teaches forming a passivation layer (Furukawa, Fig. 18, ¶0033-¶0034, ¶0040-¶0042, ¶0064-¶0065, ¶0068) for a semiconductor element including n-GaN layer (112), wherein the passivation layer includes a plurality of silicon oxide films (e.g., 132/134 and 232/234) having high density and low denisty, wherein the insulating film comprises the first SiO2 layer (134) (Furukawa, Fig. 18, ¶0042) having lower density and the second SiO2 layer (232) (Furukawa, Fig. 18, ¶0064) having higher density in order from the semiconductor layer (112) to protect the semiconductor element from moisture and metal ions (Furukawa, ¶0064-¶0065).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the manufacturing method for the semiconductor element of Ueno/Furukawa/Uemura by forming a passivation layer including a plurality of silicon oxide (SiO2) layers having different densities as taught by Furukawa to have the manufacturing method for the semiconductor element, wherein the insulating film comprises the first SiO2 layer and the second SiO2 layer in order from the semiconductor layer, in order to improve passivation performance, and to protect the semiconductor element from moisture and metal ions (Furukawa, ¶0064-¶0065).
Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over US 2013/0328120 to Ueno in view of Furukawa (US 2019/0260178) and Uemura (US 2013/0278855) as applied to claim 7, and further in view of Hasegawa et al. (US 2016/0254392, cited in IDS of 08/26/2024, hereinafter Hasegawa).
Regarding claim 10, Ueno in view of Furukawa and Uemura discloses the manufacturing method for the semiconductor element, according to claim 7. Further, Ueno discloses that the insulating film (e.g., Al2O3/SiO2 or SiO2/Al2O3) (Ueno, Fig. 1, ¶0050) further comprises an Al2O3 layer, but does not specifically disclose that, the Al2O3 layer is formed by an atomic layer deposition method.
However, Hasegawa teaches forming the insulating film including the Al2O3 layer (160) (Hasegawa, Fig. 1, ¶0011, ¶0047, ¶0051-¶0052) formed by an atomic layer deposition (ALD) method on side surfaces (112s) of mesa and top electrode (150) to ensure tightness of contact between the top electrode (150) and the insulating film (160), to suppress the leakage current (Hasegawa, Fig. 1, ¶0011).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the manufacturing method for the semiconductor element of Ueno/Furukawa/Uemura by forming a passivation layer including the Al2O3 layer formed by a deposition method as taught by Hasegawa to have the manufacturing method for the semiconductor element, wherein the Al2O3 layer is formed by an atomic layer deposition method, in order to ensure tightness of contact between the top electrode and the insulating film to suppress the leakage current (Hasegawa, ¶0011, ¶0051-¶0052).
Regarding claim 11, Ueno in view of Furukawa, Uemura, and Hasegawa discloses the manufacturing method for the semiconductor element, according to claim 10. Further, Ueno discloses the manufacturing method for the semiconductor element, wherein the insulating film (e.g., Al2O3/SiO2) (Ueno, Fig. 1, ¶0050) comprises the Al2O3 layer and the SiO2 layer in order from the semiconductor layer (11).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over US 2013/0328120 to Ueno in view of Furukawa (US 2019/0260178) and Uemura (US 2013/0278855) as applied to claim 7, and further in view of Miyoshi et al. (US 2010/0220760, hereinafter Miyoshi).
Regarding claim 12, Ueno in view of Furukawa and Uemura discloses the manufacturing method for the semiconductor element, according to claim 7. Further, Ueno does not specifically disclose the method, further comprising, after the insulating film is formed, locally dry-etching the side wall portion of the insulating film.
However, Miyoshi teaches a method of forming nitride semiconductor device (Miyoshi, Figs. 1(a)-1(b), ¶0014-¶0019, ¶0027-¶0036) comprising a protective film having a smaller thickness on both sides of the mesa/ridge than that on the surface of the semiconductor layer adjacent the sides of the mesa/ridge, to improve performance of the device, wherein after the insulating film (30) (Miyoshi, Figs. 1(a)-1(b), ¶0036) is formed, locally dry-etching the side wall portion of the insulating film (30) to partially reduce the thickness of the insulating layer (30) to form regions of smaller thickness at the sidewalls of the mesa/ridge (24), to provide a nitride semiconductor device with secured adhesion of the protective film to both sides of the ridge and improved performance characteristics (Miyoshi, ¶0008-¶0010, ¶0036).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the manufacturing method for the semiconductor element of Ueno/Furukawa/Uemura by forming a passivation layer having a smaller thickness on both sides of the mesa/ridge as taught by Miyoshi to have the manufacturing method for the semiconductor element, further comprising, after the insulating film is formed, locally dry-etching the side wall portion of the insulating film, in order to provide a nitride semiconductor device with secured adhesion of the protective film to both sides of the ridge and improved performance characteristics (Miyoshi, ¶0008-¶0010, ¶0036).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATALIA GONDARENKO whose telephone number is (571)272-2284. The examiner can normally be reached 9:30 AM-7:30 PM.
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/NATALIA A GONDARENKO/ Primary Examiner, Art Unit 2891
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