DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4 and 6-10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2022/0046795 A1 (Ikeda).
Ikeda discloses, referring primarily to figures 1-3, a wiring board (100) comprising: an insulation layer (4) having a first surface and a second surface opposite to the first surface; and a first wiring conductor (3, 3a) located on the first surface, wherein the first surface of the insulation layer comprises a first region (4u) having a first arithmetic mean roughness and a second region (4c) having a second arithmetic mean roughness, the second arithmetic mean roughness is larger than the first arithmetic mean roughness ([0053]), and the first wiring conductor is located from the first region to the second region (figure 2) [claim 1], wherein the second region comprises a recessed portion recessed toward the second surface (figure 3) [claim 2], further comprising a second wiring conductor (11) located on the second surface, wherein in a plane perspective, the second wiring conductor is located overlapping the first region (figure 1) [claim 3], wherein a depth of the recessed portion is 5 µm or less at a deepest portion ([0051]-[0052]) [claim 4], wherein the second arithmetic mean roughness is at least 1.5 times the first arithmetic mean roughness ([0053]) [claim 6], wherein the first region and the second region are alternately located along the first wiring conductor (figure 2) [claim 7], wherein the first wiring conductor is a signal conductor ([0047]) [claim 8], wherein a third arithmetic mean roughness of a side surface of the first wiring conductor and a surface, of the first wiring conductor, located opposite to a surface in contact with the first surface is smaller than the first arithmetic mean roughness (only the insulating layer is subjected to a roughening treatment so the wiring layers are, relatively, smooth [0062]-[0064]) [claim 9].
Furthermore, Ikeda discloses, a mounting structure comprising: the wiring board according to claim 1 (as described above); and an element located on a surface of the wiring board (not shown, but referenced in [0028]) [claim 10].
Claim Objections
Claim 5 is objected to under 37 CFR 1.75(c) as being in improper form because a multiple dependent claim must only refer to preceding claims in the alternative only. As currently drafted, the phrase “according to any one of claims” may refer to both preceding and following claims and is thus improper. See MPEP § 608.01(n). Accordingly, the claim has not been further treated on the merits.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEREMY C NORRIS whose telephone number is (571)272-1932. The examiner can normally be reached 7:15-15:15 M-F.
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JEREMY C. NORRIS
Examiner
Art Unit 2847
/JEREMY C NORRIS/ Primary Examiner, Art Unit 2847