DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3 and 4 is/are rejected under 35 U.S.C. 102(a)(1) as being Anticipated by TAMURA et al. (US 2016/0043073), (hereinafter, TAMURA).
RE Claim 1, TAMURA discloses an IGBT is disposed in an IGBT portion, and an FWD “free wheel diode” is disposed in an FWD portion. A p-type base region and an n− - type drift region are alternately exposed in a trench longitudinal direction in a substrate front surface in a mesa portion between neighboring trenches in the IGBT portion. A p-type anode region and the n− - type drift region are alternately exposed in the trench longitudinal direction in the substrate front surface in a mesa portion in the FWD portion, and a repetitive structure is formed with a portion of the n− - type drift region sandwiched between p-type anode regions and one p-type anode region in contact with the portion as one unit region. The proportion occupied by the p-type anode region in one unit region (an anode ratio) (α) is 50% to 100%. TAMURA discloses in FIGS. 1-18 a semiconductor device comprising an RC-IGBT having an IGBT unit 21 and a diode unit 22 “FWD” formed in a single chip, wherein:
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a collector electrode layer/cathode electrode layer 13, a diffusion layer “Lp”, a buffer layer 11, a drift layer 1, a body layer 5-1/5-2, an insulating layer 8, and an emitter/anode electrode layer 9 are stacked in the order from a back surface side to a front surface side of the chip, referring to FIG. 2;
the diode unit 22 includes a plurality of trenches 2; and
the plurality of trenches 2 include a region in the presence of the body layer 5-2 between the trenches 2, and a region in the absence of the body layer between the trenches, referring to FIG. 2.
RE Claim 3, TAMURA discloses a semiconductor device, The semiconductor device according to wherein an area of the body layer “anode region” 5-2 is 50% of an area of the cathode electrode layer 12 or smaller in a planar view of the diode unit 22, referring to FIGS. 1 and 2 [abstract, 0036, 0047 and 0052].
RE Claim 4, TAMURA discloses a semiconductor device, The semiconductor device according to wherein the plurality of trenches 2 in the region in the absence of the body layer are arranged at a boundary between the IGBT unit 21 and the diode unit 22, referring to FIGS. 1 and 2.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over ARAI et al. (US 2017/0317075), (hereinafter, ARAI) in view of TAMURA et al. (US 2016/0043073), (hereinafter, TAMURA).
RE Claim 5, ARAI discloses in FIG.12 a power conversion device including:
a pair of DC terminals 9 “Vcc”;
AC terminals, the number of which is the same as the number of 3 phases 910/911/912 of an AC output;
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switching legs “3-switching legs”, referring to FIG. 12, the number of which is the same as the number of phases of the 3 AC output, the switching leg being connected between the pair of DC terminals 900, and the switching leg including two parallel circuits connected in series , referring to FIG. 12, and each of the two parallel circuits being formed of a switching element IGBT “701/702/703/704/705/706”and a diode “711/712/713/714/715/716” connected reversely in parallel to the switching element, referring to FIG. 12; and
a gate circuit 801-08 for controlling the switching element 701-706, wherein the diode 711-716 and the switching element 701-706 constitute the semiconductor device.
ARAI does not disclose that the gate circuit 801-08 for controlling the switching element 701-706, wherein the diode 711-716 and the switching element 701-706 constitute the semiconductor device according to Claim 1.
However, in the same field of endeavor, TAMURA discloses an integrated IGBT/diode structure on one chip as detailed in Claim 1, referring to Claim 1 rejection above.
Therefore, it would have been obvious for one of ordinary skill in the art, prior to the effective filing date of the instant application to have a gate circuit 801-08 for controlling the switching element 701-706, wherein the diode 711-716 and the switching element 701-706 constitute the semiconductor device of ARAI, according to TAMURA discloses an integrated IGBT/diode structure 21/22 of Claim 1 above in order to achieve integrated function controlling the overall power conversion device performance.
Allowable Subject Matter
Claim 2 is objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YASSER ABDELAZIEZ whose telephone number is (571)270-5783. The examiner can normally be reached Monday - Friday 9 am - 6 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at (571)270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YASSER A ABDELAZIEZ, PhD/Primary Examiner, Art Unit 2898
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