Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1. This office acknowledges receipt of the following item(s) from the Applicant:
Information Disclosure Statement (IDS) was considered.
Papers submitted under 35 U.S.C. 119(a)-(d) have been placed of record in the file.
2. Claims 1-5 are presented for examination.
Title
3. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
4. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
6. Claims 1-2 and 4 are rejected under 35 U.S.C. § 102(a)(1) as being anticipated by Moriwaki US Pub. No. 20130039120.
As per claim 1, Fig. 4 of Moriwaki is directed to a semiconductor device comprising: a first circuit (GPC, connecting to GPRE; ETr and ETrX, par63), a second circuit (KP in Sub BLK B00, pars. 58 and 60), a third circuit (C0, par. 60), a fourth circuit (EQ and SA, par. 67)), a first wiring (GBL0, par. 64), a second wiring (GBLX0), a third wiring (RD0), a fourth wiring (RDX0), and a fifth wiring (LBL), wherein the first circuit is electrically connected to the second circuit through the first wiring, wherein the first circuit is electrically connected to the fourth circuit through each of the third wiring and the fourth wiring, wherein the second circuit is electrically connected to the third circuit through the fifth wiring, wherein the first circuit is configured to establish or break electrical continuity (by control signals GPRE and SAE) among the first wiring, the second wiring, the third wiring, and the fourth wiring, wherein the third circuit is configured to retain a potential corresponding to first data (by C0), wherein the second circuit is configured to supply the potential corresponding to the first data from the first wiring to the fifth wiring, to retain a potential corresponding to second data (from LBL), and to amplify (by KP)a change in a potential of the fifth wiring and output the amplified change to the first wiring, and wherein the fourth circuit is configured to output the potential corresponding to the first data or the second data in accordance with a potential difference between the third wiring and the fourth wiring (by SA).
As per claim 2, Fig. 4 of Moriwaki discloses wherein the first circuit comprises a first transistor (a transistor connecting to GBL0 and GBLX0), a second transistor (ETr), a third transistor (ETrX), a fourth transistor (a transistor in GPC connecting to GBL0 and a power voltage) , and a fifth transistor (a transistor in GPC connecting to GBLX0 and a power voltage), wherein the first transistor has a function of establishing or breaking is configured to establish or break electrical continuity between the first wiring and the second wiring, wherein the second transistor has a function of establishing or breaking is configured to establish or break electrical continuity between the first wiring and the third wiring, wherein the third transistor has a function of establishing or breaking is configured to establish or break electrical continuity between the second wiring and the fourth wiring, wherein the fourth transistor has a function of precharging is configured to precharge the first wiring, and wherein the fifth transistor has a function of precharging is configured to precharge the second wiring.
As per claim 4, Fig. 4 of Moriwaki discloses wherein the first circuit comprises a first transistor (a transistor connecting to GBL0 and GBLX0), a second transistor (ETr), and a third transistor (ETrX), wherein the first transistor has a function of establishing or breaking is configured to establish or break electrical continuity between the first wiring and the second wiring, wherein the second transistor has a function of establishing or breaking is configured to establish or break electrical continuity between the first wiring and the third wiring, wherein the third transistor has a function of establishing or breaking is configured to establish or break electrical continuity between the second wiring and the fourth wiring, wherein the fourth circuit comprises a sixth transistor (a transistor in EQ connecting to RD0 and a power supply) and a seventh transistor (a transistor in EQ connecting to RD0 and a power supply), wherein the sixth transistor has a function of precharging is configured to precharge the third wiring, and wherein the seventh transistor has a function of precharging is configured to precharge the fourth wiring.
Allowable Subject matter
7. Claims 3 and 5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
8. The following is a statement of reasons for the indication of allowable subject matter:
Claims include allowable subject matter since the prior art made of record and considered pertinent to the applicants’ disclosure, taken individually or in combination, does not teach or suggest the claimed invention having wherein the first circuit comprises a first transistor, a second transistor, a third transistor, a first capacitor, and a second capacitor, wherein the first transistor is configured to establish or break electrical continuity between the first wiring and the second wiring, wherein the second transistor is configured to establish or break electrical continuity between the first wiring and the third wiring, wherein the third transistor is configured to establish or break electrical continuity between the second wiring and the fourth wiring, wherein the first capacitor is configured to change a potential of the first wiring, and wherein the second capacitor is configured to change a potential of the second wiring in a claim 3; wherein the fourth circuit is provided in a substrate, wherein the first circuit and the second circuit are provided in a first layer placed over the substrate, wherein the third circuit is provided in each of a plurality of second layers placed over the substrate, wherein the substrate comprises a Si transistor, and wherein each of the first layer and the plurality of second layers comprises an OS transistor in claim 5.
9. When responding to the office action, Applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner to locate the appropriate paragraphs.
10. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the date of this letter. Failure to respond within the period for response will cause the application to become abandoned (see MPEP 710.02 (b)).
11. Any inquiry concerning this communication or earlier communications from the examiner should be directed to HOAI V HO whose telephone number is (571)272-1777. The examiner can normally be reached 7:00 AM -- 5:30 PM from Thursday and Friday of the first week of a bi-week and Tuesday and Wednesday of the second week.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached on (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is (571)-273-8300.
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/HOAI V HO/Primary Examiner, Art Unit 2827
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