DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 14-16 and 20 are objected to because of the following informalities: Claims 14 and 15 both depend from cancelled dependent claim 2. It is hard to determine which preceding claim that claims 14 and 15 should depend from. For the purpose of examination, the Examiner will take claims 14 and 15 to be dependent upon independent claim 1. Claims 16 and 20 inherit these deficiencies due to their dependency. . Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (Yang) (CN 113314474 A) in view of Tao (CN 103745958 A) [See first and second office action for Chinese Application 202310959645 7].
In regard to claim 1, Yang (Abstract, paragraphs 26-34, Fig. 1 and associated text) discloses a method of preparing an all-glass stacked packaging structure, comprising following steps: S1: providing an embedded chip fan-out packaging structure (Fig. 1) provided with a glass substrate (items 1, 5, 7, 8 or 1 plus 5 plus 7 plus 8) and a glass metallized circuit structure (items 2, 3, 2 and 3 plus 1, 5, 7 or 8) provided with a glass substrate (items 1, 5, 7, 8,), and butt-joining and securing by welding a metal bump (shown but not labeled) of the embedded chip fan-out packaging structure to an exposed second redistribution layer (items 1 or 8) of the glass metallized circuit structure (items 2, 3, 2 and 3 plus 1, 5, 7 or 8); but does specifically disclose S2: filling a gap between the embedded chip fan-out packaging structure and the glass metallized circuit structure with a connecting material, and carrying out sintering on the connecting material at 160-300° C. for 0.5-4 h to obtain the all-glass stacked packaging structure, wherein the connecting material is a solid inorganic silicate; wherein the inorganic silicate is Na.sub.2O.Math.nSiO.sub.2, wherein n=0.1-5.
Tao (paragraphs 25-80, Figs. 1-11 and associated text) discloses a filling layer (item 209) that fills the space between a first surface (item 11) of the circuit carrier board (item 100), thus S2: filling a gap between the embedded chip fan-out packaging structure and the glass metallized circuit structure with a connecting material (item 209), and carrying out sintering on the connecting material (item 209) at 160-300° C. for 0.5-4 h to obtain the all-glass stacked packaging structure, wherein the connecting material (item 209) is a solid inorganic silicate (epoxy resin, polyimide resin, benzocyclobutene resin or polybenzoxazole resin [equivalent to a compound without alkali metal] or other suitable materials); wherein the inorganic silicate is Na.sub.2O.Math.nSiO.sub.2, wherein n=0.1-5. “It can be seen that Tao discloses that the reliability of the fixed connection between the pre-packaged structure and the carrier board is improved by filling the gap between the pre-packaged structure and the carrier board with a filling layer (item 209). Sinter molding is a commonly used technical means in the art, and it does not bring unexpected technical effects. The type of the connecting material, the sintering temperature and the sintering time can be set by those skilled in the art according to the actual needs. For example, when the connecting material is an inorganic silicate, the connecting material is sintered at 160-300 °C for 0.5-4 h, where the inorganic silicate is Na₂O .nSiO₂, where n = 0.1-5, which is a commonly used technical means in the art and does not bring unexpected technical effects”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Tao for the purpose of fixed connection.
In regard to claim 19, Yang (Abstract, paragraphs 26-34, Fig. 1 and associated text) as modified by Tao (paragraphs 25-80, Figs. 1-11 and associated text) discloses an all-glass stacked packaging structure prepared by using the preparation method according to claim 1, comprising an embedded chip fan-out packaging structure (Fig. 1) and a glass metallized circuit structure (items 2, 3, 2 and 3 plus 1, 5, 7 or 8) that are stacked vertically, wherein a metal bump a metal bump (shown but not labeled) of the embedded chip fan-out packaging structure to an exposed second redistribution layer (items 1 or 8) of the glass metallized circuit structure (items 2, 3, 2 and 3 plus 1, 5, 7 or 8); but does specifically disclose a gap between the embedded chip fan-out packaging structure and the glass metallized circuit structure is filled with a connection layer formed by sintering a connecting material.
Tao (paragraphs 25-80, Figs. 1-11 and associated text) discloses a filling layer (item 209) that fills the space between a first surface (item 11) of the circuit carrier board (item 100), thus S2: filling a gap between the embedded chip fan-out packaging structure and the glass metallized circuit structure with a connecting material (item 209), and carrying out by sintering a connecting material (item 209, epoxy resin, polyimide resin, benzocyclobutene resin or polybenzoxazole resin [equivalent to a compound without alkali metal] or other suitable materials).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Tao for the purpose of fixed connection.
Claim(s) 3-11 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (Yang) (CN 113314474 A) in view of Tao (CN 103745958 A) as applied to claim 1 above and further in view of Chen et al. (Chen) (US 2022/0013462 A1) [See first and second office action for Chinese Application 202310959645 7].
In regard to claim 3, Yang (Abstract, paragraphs 26-34, Fig. 1 and associated text) as modified by Tao does not specifically disclose wherein in step S1, a method of preparing the embedded chip fan-out packaging structure (Fig. 1) comprises following steps: S10: providing a first glass substrate, and opening on the first glass substrate a number of embedded grooves with a design size larger than a size of a chip; S20: attaching a first surface of the first glass substrate onto a temporary adhesive film, and attaching the chip into an embedded groove of the embedded grooves; S30: separately preparing a dielectric layer on the first surface of the first glass substrate and a second surface of the first glass substrate, and processing the dielectric layer to expose an I/O port of a chip to obtain a chip package; S40: carrying out hole opening on the chip package to form a number of through holes penetrating through the chip package; and S50: electrically leading the I/O port of the chip via a through hole of the through holes out of both surfaces of the chip package synchronously to obtain the embedded chip fan-out packaging structure.
Chen (paragraphs 41-52, Figs. 1-9 and associated text) discloses “providing a glass frame 100 (equivalent to the first glass substrate), and opening a plurality of embedding grooves 120 with design sizes larger than the chip size and a plurality of through holes penetrating the glass frame 100 on the glass frame 100; The first surface of the glass frame 100 is attached to the adhesive tape 900 (equivalent to a temporary adhesive film), and the chip 200 is attached to the embedding groove 120; A dielectric layer 300 is prepared on the second side of the glass frame 100 to produce a chip package; The I/O port of the chip 200 is electrically and synchronously led out from both sides of the chip package through the through hole, and an embedded chip fan-out package structure is manufactured. Chen has disclosed the double-sided fan-out structure of embedded chips. On the basis of the above, technicians in this field can set dielectric layers according to actual needs, such as preparing dielectric layers on both the first and second sides of the substrate, which is a common technical means in this field and has not brought unexpected technical effects. In order to realize external electrical connection, when the I/O port of the chip is covered with a dielectric layer, the technicians in this field usually treat the dielectric layer to expose the I/O port of the chip, which is a common technical means in this field and has not brought unexpected technical effects. The order of the formation of the through holes can be set by the technicians in the field according to the actual needs. For example, after the dielectric layer is formed, the chip package is perforated to form a plurality of through holes, which is a common technical means in the field and has not brought unexpected technical effects”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Chen for the purpose of protection and an electrical connection.
In regard to claim 4, Yang (Abstract, paragraphs 26-34, Fig. 1 and associated text) as modified by Tao and Chen (paragraphs 41-52, Figs. 1-9 and associated text) discloses wherein in step S20, the I/O port (item 600, 420 or 600 plus 420) of the chip (item 200) protrudes out of a surface of the chip (item 200), and after the chip (item 200) is attached into the embedded groove with a front surface of the chip facing upwards, step S30 specifically comprises following steps: S30a: preparing a first dielectric layer on the second surface of the first glass substrate; S30b: thinning, by grinding, the first dielectric layer to expose the I/O port of the chip; S30c: removing the temporary adhesive film; and S30d: preparing a second dielectric layer on the first surface of the first glass substrate to obtain the chip package. “The placement of the active surface of the chip can be set by the technicians in the field according to the actual needs, such as placing the chip. It is a common technical means in the field that the source surface is stuck in the embedding groove with the front face facing upwards, which has not brought unexpected technical effects. On the basis of the double-sided fan-out structure of the embedded chip disclosed by Yang as modified by Tao, it is easy to obtain the technical scheme that after the chip is stuck in the embedded groove with the front face facing upwards, the first dielectric layer is prepared on the second face of the first glass substrate, and the first dielectric layer is ground and thinned to expose the I/O port of the chip, and the temporary adhesive film is removed, and the second dielectric layer is prepared on the first face of the first glass substrate, thus making the chip package”.
In regard to claim 5, Yang (Abstract, paragraphs 26-34, Fig. 1 and associated text) as modified by Tao and Chen (paragraphs 41-52, Figs. 1-9 and associated text) discloses wherein in step S20, the I/O port of the chip is flush with a surface of the chip, and after the chip is attached into the embedded groove with a front surface of the chip facing upwards, step S30 specifically comprises following steps: S30a: preparing a first dielectric layer on the second surface of the first glass substrate; S30b: carrying out laser drilling on the first dielectric layer to expose the I/O port of the chip; S30c: removing the temporary adhesive film; and S30d: preparing a second dielectric layer on the first surface of the first glass substrate to obtain the chip package. “The relative position between the I/O port of the chip and the surface of the chip can be set by the technicians in the field according to the actual needs, such as the I/O port of the
chip is flush with the surface of the chip, which is a common technical means in the field and has not brought unexpected technical effects. The placement mode of the active surface of the chip can be set by the technicians in the field according to the actual needs, such as sticking the active surface of the chip in the embedding groove with the front face facing upwards, which is a common technical means in the field and has not brought unexpected technical effects. On the basis of the double-sided fan-out structure of the embedded chip disclosed by Yang in view of Tao, it is easy to obtain the technical scheme that after the chip is stuck in the embedded groove with the front face facing upwards, the first dielectric layer is prepared on the second face of the first glass substrate, and the first dielectric layer is subjected to laser hole opening treatment to expose the I/O port of the chip, and the temporary adhesive film is removed, and the second dielectric layer is prepared on the first face of the first glass substrate to prepare the chip package”.
In regard to claim 6, Yang (Abstract, paragraphs 26-34, Fig. 1 and associated text) as modified by Tao and Chen (paragraphs 41-52, Figs. 1-9 and associated text) discloses that the front face of the chip 200 is attached to the chip embedding cavity 120. The relative position between the I/O port of the chip and the surface of the chip can be set by the technicians in the field according to the actual needs, such as the I/O port of the chip is flush with the surface of the chip, which is a common technical means in the field and has not brought unexpected technical effects. On the basis of the double-sided fan-out structure of embedded chip disclosed by Yang in view of Tao, combined with the common technical means in this field, it is easy to obtain the technical scheme of preparing the first dielectric layer on the second side of the first glass substrate, removing the temporary adhesive film, preparing the second dielectric layer on the first side of the first glass substrate, and laser drilling the second dielectric layer to expose the I/O port of the chip to make the chip package”. Thus, wherein in step S20, the I/O port of the chip is flush with a surface of the chip, and when the chip is attached into the embedded groove with a front surface of the chip facing downwards, step S30 specifically comprises following steps: S30a: preparing a first dielectric layer on the second surface of the first glass substrate; S30b: removing the temporary adhesive film; S30c: preparing a second dielectric layer on the first surface of the first glass substrate; and S30d: carrying out laser drilling on the second dielectric layer to expose the I/O port of the chip to obtain the chip package.
In regard to claim 7, Yang (Abstract, paragraphs 26-34, Fig. 1 and associated text) as modified by Tao and Chen (paragraphs 41-52, Figs. 1-9 and associated text) discloses wherein step S50 comprises following steps: S50a: preparing a seed layer (item 600) on a surface of the chip package and an inner wall of the through hole (item 110); S50b: attaching a photosensitive film (item 420) onto the seed layer (item 600) on the surface of the chip package, and carrying out exposure and development to form a patterned window; S50c: preparing a first redistribution layer in the patterned window and on an inner wall of the through hole; S50d: removing a residual photosensitive film and etching away an exposed seed layer; S50e: preparing a solder mask in the through hole and on both surfaces of the chip package prepared with the first redistribution layer, and exposing a pad region of the first redistribution layer; and S50f: preparing a nickel-palladium-gold layer in the pad region of the first redistribution layer, and implanting a metal bump in the nickel-palladium-gold layer to obtain the embedded chip fan-out packaging structure. Chen (paragraphs 41-52, Figs. 1-9 and associated text) discloses that a metal seed layer 600 is fabricated on the surface of the chip package and the inner wall of the second through hole; After the seed layer is formed, a photosensitive barrier layer 800 (equivalent to a photosensitive film) is attached to the surface of the seed layer, and the photosensitive barrier layer 800 is patterned to expose the circuit layer 420 and the through hole 110 (equivalent to sticking a photosensitive film on the seed layer on the surface of the chip package, forming a patterned window after exposure and development, and preparing a first rewiring layer in the patterned window and the inner wall of the through hole); As shown in fig. 8, organic or inorganic materials are used. The stripping solution is stripped to remove the photosensitive barrier layer 800, and the metal seed layer 600 is etched to keep the metal seed layer 600 consistent with the circuit layer 420. (equivalent to removing the residual photosensitive film and etching away the exposed seed layer); Solder-resist layers 500 are prepared on both sides of the chip package with the first rewiring layer, and the pad areas 510 of the first rewiring layer are exposed, thus making the embedded chip fan-out package structure.
In regard to claim 8, Yang (Abstract, paragraphs 26-34, Fig. 1 and associated text) as modified by Tao and Chen (paragraphs 41-52, Figs. 1-9 and associated text) discloses wherein in step S1, a method of preparing the embedded chip fan-out packaging structure comprises following steps: S10: providing a first glass substrate, and opening on the first glass substrate a number of first through holes and a number of embedded grooves with a design size larger than a size of a chip; S20: attaching a first surface of the first glass substrate onto a temporary adhesive film, and attaching the chip into an embedded groove of the embedded grooves; S30: preparing a dielectric layer on each of the first surface of the first glass substrate and a second surface of the first glass substrate, filling a first through hole of the first through holes and a gap between the chip and the first glass substrate with the dielectric layer, and processing the dielectric layer to expose an I/O port of a chip to obtain a chip package; S40: opening a second through hole on the dielectric layer filled in the first through hole; and S50: electrically leading the I/O port of the chip via the second through hole out of both surfaces of the chip package synchronously to obtain the embedded chip fan-out packaging structure.
Chen (paragraphs 41-52, Figs. 1-9 and associated text) discloses “that, as can be seen from Figures 1-9, a glass frame 100 (equivalent to the first glass substrate) is provided, and a plurality of first through holes 110 and a plurality of chip embedding cavities 120 (equivalent to embedding grooves) with a design size larger than the chip size are formed on the glass frame 100; The first surface of the glass frame 100 is attached to the temporary adhesive film 900, and the chip 200 is attached to the chip embedding cavity 120; A dielectric layer 300 is prepared on the second side of the glass frame 100, and the dielectric layer 300 is filled in the first through hole 110 and the gap between the chip 200 and the glass frame 100, so as to prepare a chip package; Opening a second through hole at the dielectric layer 300 filled in the first through hole 110. As shown in fig. 6, the adhesive tape 900 stuck on the lower surface of the glass frame 100 is removed, and the metal seed layer 600 is manufactured on the upper and lower surfaces of the glass frame 100 so that the metal seed layer 600 covers the sidewall of the first through hole 110, and the metal copper covers the through hole 110 and the upper surface of the metal seed layer 600 at a specific position. So as to form the metal pillar 410 and the circuit layer 420 (which is equivalent to leading the I/O port of the chip out of the double sides of the chip package through the second through hole synchronously and electrically, and making the embedded chip fan-out package structure). Chen has already disclosed the double-sided fan-out structure of embedded chips. On the basis of the above, technicians in this field can set dielectric layers according to actual needs, such as preparing dielectric layers on both the first and second sides of the first glass substrate, which is a common technical means in this field and has not brought unexpected technical effects. In order to realize external electrical connection, in the case that the
I/O port of the chip is covered by a dielectric layer, a person skilled in the art will usually
Treating the dielectric layer to expose the I/O port of the chip is a common technical means in this field, which has not brought unexpected technical effects.
In regard to claim 9, Yang (Abstract, paragraphs 26-34, Fig. 1 and associated text) as modified by Tao and Chen (paragraphs 41-52, Figs. 1-9 and associated text) discloses wherein in step S20, the I/O port of the chip protrudes out of a surface of the chip, and after the chip is attached into the embedded groove with a front surface of the chip facing upwards, step S30 specifically comprises following steps: S30a: preparing a first dielectric layer on the second surface of the first glass substrate; S30b: thinning, by grinding, the first dielectric layer to expose the I/O port of the chip; S30c: removing the temporary adhesive film; and S30d: preparing a second dielectric layer on the first surface of the first glass substrate to obtain the chip package. . Chen discloses “that, as can be seen from Figure 9, I/O of chip 200. The mouth protrudes from the surface of the chip 200. The placement of the active surface of the chip can be set by the technicians in the field according to the actual needs, such as placing the chip. It is a common technical means in the field that the source surface is stuck in the embedding groove with the front face facing upwards, which has not brought unexpected technical effects. On the basis of the double-sided fan-out structure of the embedded chip disclosed in Yang in view of Tao, it is easy to obtain the technical scheme that after the chip is stuck in the embedded groove with the front face facing upwards, the first dielectric layer is prepared on the second face of the first glass substrate, and the first dielectric layer is ground and thinned to expose the I/O port of
the chip, and the temporary adhesive film is removed, and the second dielectric layer is prepared on the first face of the first glass substrate, thus making the chip package”.
In regard to claim 10, Yang (Abstract, paragraphs 26-34, Fig. 1 and associated text) as modified by Tao and Chen (paragraphs 41-52, Figs. 1-9 and associated text) discloses wherein in step S20, the I/O port of the chip is flush with a surface of the chip, and after the chip is attached into the embedded groove with a front surface of the chip facing upwards, step S30 specifically comprises following steps: S30a: preparing a first dielectric layer on the second surface of the first glass substrate; S30b: carrying out laser drilling on the first dielectric layer to expose the I/O port of the chip; S30c: removing the temporary adhesive film; and S30d: preparing a second dielectric layer on the first surface of the first glass substrate to obtain the chip package. “The relative position between the I/O port of the chip and the surface of the chip can be set by the technicians in the field according to the actual needs, such as the I/O port of the
chip is flush with the surface of the chip, which is a common technical means in the field and has not brought unexpected technical effects. The placement mode of the active surface of the chip can be set by the technicians in the field according to the actual needs, such as sticking the active surface of the chip in the embedding groove with the front face facing upwards, which is a common technical means in the field and has not brought unexpected technical effects. On the basis of the double-sided fan-out structure of the embedded chip disclosed by Yang in view Tao, it is easy to obtain the technical scheme that after the chip is stuck in the embedded groove with the front face facing upwards, the first dielectric layer is prepared on the second face of the first glass substrate, and the first dielectric layer is subjected to laser hole opening treatment to expose the I/O port of the chip, and the temporary adhesive film is removed, and the second dielectric layer is prepared on the first face of the first glass substrate to prepare the chip package”.
In regard to claim 11, Yang (Abstract, paragraphs 26-34, Fig. 1 and associated text) as modified by Tao and Chen (paragraphs 41-52, Figs. 1-9 and associated text) discloses wherein in step S20, the I/O port of the chip is flush with a surface of the chip, and when the chip is attached into the embedded groove with a front surface of the chip downwards, step S30 specifically comprises following steps: S30a: preparing a first dielectric layer on the second surface of the first glass substrate; S30b: removing the temporary adhesive film; S30c: preparing a second dielectric layer on the first surface of the first glass substrate; and S30d: carrying out laser drilling on the second dielectric layer to expose the I/O port of the chip to obtain the chip package. Chen “discloses that the front face of the chip 200 is attached to the chip embedding cavity 120. The relative position between the I/O port of the chip and the surface of the chip can be set by the technicians in the field according to the actual needs, such as the I/O port of the chip is flush with the surface of the chip, which is a common technical means in the field and has not brought unexpected technical effects. On the basis of the double-sided fan-out structure of embedded chip disclosed by Yang as modified by Tao and Chen, combined with the common technical means in this field, it is easy to obtain the technical scheme of preparing the first dielectric layer on the second side of the first glass substrate, removing the temporary adhesive film, preparing the second dielectric layer on the first side of the first glass substrate, and laser drilling the second dielectric layer to expose the I/O port of the chip to make the chip package.
In regard to claim 13, Yang (Abstract, paragraphs 26-34, Fig. 1 and associated text) as modified by Tao and Chen (paragraphs 41-52, Figs. 1-9 and associated text) discloses wherein in step S40, the second through hole (item 110) is opened by photoligraphy on the dielectric layer (item 300) filled in the first through hole, however laser forming/etching through holes is a common technical means in this field, which has not yielded unexpected technical effects.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (Yang) (CN 113314474 A) in view of Tao (CN 103745958 A) in view of Chen et al. (Chen) (US 2022/0013462 A1) as applied to claims 3-11 above and further in view of Lin et al. (Lin) (CN 211150550 U) [See first and second office action for Chinese Application 202310959645 7].
In regard to claim 12, Yang (Abstract, paragraphs 26-34, Fig. 1 and associated text) as modified by Tao and Chen (paragraphs 41-52, Figs. 1-9 and associated text) discloses wherein step S50 specifically comprises following steps: S50a: preparing a seed layer on a surface of the chip package and an inner wall of the second through hole; S50b: attaching a photosensitive film onto the seed layer on the surface of the chip package, and carrying out exposure and development to form a patterned window; S50c: preparing a first redistribution layer in the patterned window and on the inner wall of the second through hole; S50d: removing a residual photosensitive film and etching away an exposed seed layer; S50e: preparing a solder mask in the second through hole and on both surfaces of the chip package prepared with the first redistribution layer, and exposing a pad region of the first redistribution layer; and S50f: preparing a nickel-palladium-gold layer in the pad region of the first redistribution layer, and implanting a metal bump in the nickel-palladium-gold layer to obtain the embedded chip fan-out packaging structure. Chen “discloses that a metal seed layer 600 is fabricated on the surface of the chip package and the inner wall of the second through hole; After the seed layer is formed, a photosensitive barrier layer 800 (equivalent to a photosensitive film) is attached to the surface of the seed layer, and the photosensitive barrier layer 800 is patterned to expose the circuit layer 420 and the through hole 110 (equivalent to sticking a photosensitive film on the seed layer on the surface of the chip package, forming a patterned window after exposure and development, and preparing a rewiring layer in the patterned window and the inner wall of the second through hole); As shown in fig. 8, organic or inorganic materials are used. The stripping solution is stripped to remove the photosensitive barrier layer 800, and the metal seed layer 600 is etched
to keep the metal seed layer 600 consistent with the circuit layer 420. (equivalent to removing the residual photosensitive film and etching away the exposed seed layer); Solder-resist layers 500 are prepared on both sides of the chip package with rewiring layers, and the pad areas 510 of the rewiring layers are exposed, SO as to manufacture the fan-out package structure of embedded chips. Another technical difference between Claim 12 is that a solder resist layer is prepared
in the second through hole, a nickel palladium gold layer is prepared in the pad area of the rewiring layer, and a metal bump is implanted in the nickel palladium gold layer. The technical problems to be solved in this claim are: protecting conductive through holes and setting external connectors. In order to protect the conductive vias, technicians in the field usually prepare solder resist layers in the conductive vias, which is a common technical means in the field and has not brought unexpected technical effects.”
Lin (paragraphs 49-107, Figs. 3-12 and associated text) disclose a method for preparing a fan-out packaging structure for embedded chips: the second electrical connection structure 51 includes a second seed layer 511 covering the second surface of the plastic packaging layer 3 and the surface of the second hole; The second rewiring layer 512 is located on the second seed layer 511, and the second seed layer 511 and the second rewiring layer 512 have a second graphic window exposing part of the second surface of the plastic packaging layer 3; The second metal bump 52 is soldered to the pad region of the second rewiring layer 512. It can be seen that Lin discloses that metal bumps are arranged on the pads of the rewiring layer as external connectors. Before forming the metal bump, the Ni-Pd-Au layer is prepared to improve the bonding wettability, which is a common technical means in this field. On the basis of combined references and common technical means in this field, it is easy to obtain the technical scheme of preparing a nickel palladium gold layer in the pad area of the rewiring layer and implanting metal bumps in the nickel palladium gold layer”.
Claim(s) 14-16 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (Yang) (CN 113314474 A) in view of Tao (CN 103745958 A) as applied to claim 1 above and further in view of Tang et al. (Tang) (CN 116313827 A) [See first and second office action for Chinese Application 202310959645 7].
In regard to claim 14, Yang (Abstract, paragraphs 26-34, Fig. 1 and associated text) as modified by Tao wherein a method of preparing the glass metallized circuit structure comprises following steps: S100: providing a second glass substrate, and carrying out laser modification on a portion of the second glass substrate; S200: pressing a photosensitive film onto both surfaces of the second glass substrate, carrying out exposure and development to form a first patterned window, and exposing a laser-modified region of the second glass substrate from the first patterned window; S300: etching the second glass substrate to form a through hole in the laser-modified region and an embedded circuit groove in a non-laser-modified region at the first patterned window; S400: removing a residual photosensitive film, and preparing a seed layer on a surface of the embedded circuit groove and an inner wall of the through hole; S500: pressing a photosensitive film onto a surface of the second glass substrate and the seed layer on the surface of the embedded circuit groove, and carrying out exposure and development on the photosensitive film to form a second patterned window; S600: preparing a conductive pillar in the through hole, and preparing in the second patterned window a second redistribution layer electrically connected to the conductive pillar, wherein a surface of the second redistribution layer is flush with the surface of the second glass substrate; S700: removing a residual photosensitive film, and carrying out flash etching on an exposed seed layer; and S800: preparing a solder mask on one side of the second glass substrate and a surface of a second redistribution layer corresponding to the one side of the second glass substrate to cover the second glass substrate and the corresponding second redistribution layer to obtain the glass metallized circuit structure.
Tang (see paragraphs [0066]- [0093] in the specification, and Figure 1-6) “discloses a method for preparing a glass metallized circuit structure: As can be seen from Figure 1-6, a glass substrate 101 (equivalent to a second glass substrate) is provided; By laser-induced etching, electrochemical method, laser ablation method, plasma etching method, focused discharge method, photosensitive glass method, sand blasting method, etc. An interconnection hole 102 (equivalent to a through hole) is formed. Sticking photoresist on both sides of the glass substrate 101, and performing exposure and development to form a first patterned window (see paragraph [0084] of the specification); Etching the glass substrate 101 to form a groove 103 (equivalent to an embedded circuit groove) in the non-laser modified area at the first patterned window (see paragraph [0084] of the specification); A metal seed layer 105 is formed on the surface of the groove 103 and the inner wall of the interconnection hole 102; A metal interconnection layer 106 (equivalent to a conductive post and a second rewiring layer) is made in the interconnection hole 102 and the groove 103, and the surface of the metal interconnection layer 106 is made flush with the surface of the glass substrate 101, thereby manufacturing a glass metallized circuit structure. It can be seen that Tang discloses that through holes are prepared on the glass substrate by laser-induced etching, and conductive columns and a second rewiring layer are formed on both sides of the glass substrate flush with the surface of the glass substrate. The laser-induced etching method usually includes modifying the region of the glass substrate where the through hole is to be formed by laser to form a laser-modified region, and then forming the through hole in the laser-modified region by etching, which is a common technical means in this field. On the basis of Tang, in order to improve the production efficiency, it is easy for technicians in this field to think of forming through holes and embedded circuit grooves on the second glass substrate at the same time, such as pressing photosensitive films on both sides of the second glass substrate, and performing exposure and development to form the first patterned window, and exposing the laser modified region of the second glass substrate to the first patterned window to etch the second glass substrate. Forming a through hole in the laser modified area and an embedded circuit groove in the non-laser modified area at the first patterned window, and removing the residual photosensitive film after forming the through hole and the embedded circuit groove, are common technical means, which have not brought unexpected technical effects”.
Therefore it would have obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Tang for the purpose of size stability, small warping deformation, high reliability, high thermal conductivity, improving the co-planarity of the substrate, improving the product yield, providing good environment for the subsequent component or chip placement, reducing the product material selection and pattern design difficulty, and reducing the production cost (Abstract).
In regard to claim 15, Yang (Abstract, paragraphs 26-34, Fig. 1 and associated text) as modified by Tao and Tang (see paragraphs [0066]- [0093] in the specification, and Figures 1-6) discloses wherein a method of preparing the glass metallized circuit structure comprises following steps: S100: providing a second glass substrate, and carrying out laser modification on a portion of the second glass substrate; S200: pressing a photosensitive film onto both surfaces of the second glass substrate, carrying out exposure and development to form a first patterned window, and exposing a laser-modified region of the second glass substrate from the first patterned window; S300: etching the second glass substrate to form a through hole in the laser-modified region and an embedded circuit groove in a non-laser-modified region at the first patterned window; S400: removing a residual photosensitive film, and preparing a seed layer on a surface of the embedded circuit groove and an inner wall of the through hole; S500: pressing a photosensitive film onto a surface of the second glass substrate and the seed layer on the surface of the embedded circuit groove, and carrying out exposure and development on the photosensitive film to form a second patterned window; S600: preparing a conductive pillar in the through hole, and preparing in the second patterned window a second redistribution layer electrically connected to the conductive pillar, wherein a surface of the second redistribution layer is flush with the surface of the second glass substrate; S700: removing a residual photosensitive film, and carrying out flash etching on an exposed seed layer; preparing a solder mask on one side of the second glass substrate and a surface of a second redistribution layer corresponding to the one side of the second glass substrate to cover the second glass substrate and the second redistribution layer; S800: preparing (m+1) first substrate structures according to steps S100-S700, wherein m is a positive integer, carrying out hole opening on a solder mask of each of m first substrate structures to expose a pad region of a second redistribution layer of each of the m first substrate structures, and implanting a metal bump in the pad region to obtain a second substrate structure serving as an intermediate; and S900: coating a metal bump of one second substrate structure with a nanometal paste, and butt-joining and securing by sintering the metal bump of the one second substrate structure to an exposed second redistribution layer of a first substrate structure; then, coating a metal bump of another second substrate structure with the nanometal paste, and butt-joining and securing by sintering the metal bump of the another second substrate structure to an exposed second redistribution layer of the one second substrate structure; securing all the second substrate structures in a same manner; finally, filling the connecting material between the first substrate structure and the second substrate structure and between each of two adjacent second substrate structures, and carrying out sintering on the connecting material to obtain the glass metallized circuit structure. Tang A plate 101 (corresponding to a second glass substrate); By laser-induced etching, electrochemical method, laser ablation method, plasma etching method, focused discharge method, photosensitive glass method, sand blasting method, etc. An interconnection hole 102 (equivalent to a through hole) is formed. Sticking photoresist on both sides of the glass substrate 101, and performing exposure and development to form a first patterned window (see paragraph [0084] of the specification); Etching the glass substrate 101 to form a groove 103 (equivalent to an embedded line) in the non-laser modified area at the first patterned window. Road groove (see paragraph [0084] of the specification); A metal seed layer 105 is formed on the surface of the groove 103 and the inner wall of the interconnection hole 102; A metal interconnection layer 106 (equivalent to a conductive post and a second rewiring layer) is made in the interconnection hole 102 and the groove 103, and the surface of the metal interconnection layer 106 is made flush with the surface of the glass substrate 101, thereby manufacturing a glass metallized circuit structure. It can be seen that reference document 5 discloses that through holes are prepared on the glass substrate by laser-induced etching, and conductive columns and a second rewiring layer are formed on both sides of the glass substrate flush with the surface of the glass substrate. The laser-induced etching method usually includes modifying the region of the glass substrate where the through hole is to be formed by laser to form a laser-modified region, and then forming the through hole in the laser-modified region by etching, which is a common technical means in this field. On the basis of Tang, in order to improve the production efficiency, it is easy for technicians in this field to think of forming through holes and embedded circuit grooves on the second glass substrate at the same time, such as pressing photosensitive films on both sides of the second glass substrate, and performing exposure and development to form the first patterned window, and exposing the laser modified region of the second glass substrate to the first patterned window to etch the second glass substrate. Forming a through hole in the laser modified area and an embedded circuit groove in the non-laser modified area at the first patterned window, and removing the residual photosensitive film after forming the through hole and the embedded circuit groove, are common technical means, which have not brought unexpected technical effects.
In regard to claims 16 and 20, Yang (Abstract, paragraphs 26-34, Fig. 1 and associated text) as modified by Tao and Tang (see paragraphs [0066]- [0093] in the specification, and Figures 1-6) does not specifically disclose wherein in step S300, an etching rate ratio of the laser-modified region to the non-laser-modified region of the second glass substrate is 20:1. The etching rate ratio of laser-modified area and non-laser- modified area of glass substrate can be controlled by technicians in the field according to actual needs. For example, the etching rate ratio of laser-modified area and non-laser-modified area of glass substrate is 20:1, which is a common
technical means in the field and has not brought unexpected technical effects.
It would have been obvious to one having ordinary skill in the art at the time of the invention to modify the invention to include an etching rate ratio of laser-modified area and non-laser-modified area of glass substrate being 20:1, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art (In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)).
Claim(s) 17 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (Yang) (CN 113314474 A) in view of Tao (CN 103745958 A) as applied to claim 1 above and further in view of Tang et al. (Tang) (CN 116313827 A) as applied to claims 14-16 above and further in view of Zeng et al. (Zeng) (CN 111315109 A) [See first and second office action for Chinese Application 202310959645 7].
In regard to claim 17, Yang (Abstract, paragraphs 26-34, Fig. 1 and associated text) as modified by Tao does not specifically disclose wherein a method of preparing the glass metallized circuit structure comprises following steps: S100: providing a second glass substrate, and carrying out laser modification on a portion of the second glass substrate; S200: etching the second glass substrate to form a through hole in a laser-modified region; S300: preparing a seed layer on an inner wall of the through hole and both surfaces of the second glass substrate; S400: separately pressing a photosensitive film onto the seed layer on the both surfaces of the second glass substrate, and carrying out exposure and development to form a patterned window; S500: preparing a second redistribution layer in the patterned window, and filling in the through hole a copper pillar connected to the second redistribution layer; S600: removing a residual photosensitive film, and carrying out flash etching on an exposed seed layer; and S700: preparing a solder mask on one side of the second glass substrate and a surface of a second redistribution layer corresponding to the one side of the second glass substrate to cover the second glass substrate and the second redistribution layer to obtain the glass metallized circuit structure.
Tang (see paragraphs [0066]- [0093] in the specification, and Figures 1-6) discloses that, as can be seen from Figure 1-2, a glass substrate 101 (equivalent to a second glass substrate) is provided; By laser-induced etching, electrochemical method, laser ablation method, plasma etching method, focused discharge method, photosensitive glass method, sand blasting method, etc. An interconnection hole 102 (equivalent to a through hole) is formed. It can be seen that Tang 5 discloses the preparation of through holes in the glass substrate by laser-induced etching. The laser-induced etching method usually includes modifying the region of the glass substrate where the through hole is to be formed by laser to form a laser- modified region. However, after that, etching is used to form a through hole in the laser modified area, which is a common technical means in this field. On the basis of Tang, it is easy to obtain by combining with common technical means in this field, such as the technical scheme of laser modifying part of the second glass substrate and forming a through hole in the laser modified area. In order to protect the rewiring layer and the surface of the glass substrate, technicians in this field usually prepare solder resist layers covering the second glass substrate and the second rewiring layer on one side of the second glass substrate and the corresponding surface. This is a common technical means in this field, which has not brought unexpected technical effects.
Zeng (paragraphs 66-71, Figs. 1A-1E and associated text) discloses “a method for preparing a glass metallized circuit structure (see paragraphs [0066]-[0071] in the specification, and figures 1A-1E): providing a glass substrate 111 (equivalent to a second glass substrate) (see figure 1a); A through hole 111c (see fig. 1A) is formed by, for example, drilling the glass substrate 111 by laser; Forming a seed layer 112 on the inner wall of the through hole 111c and the first surface 111a and the second surface 111b of the glass substrate 111 (see fig. 1b); Calendering a resist layer (equivalent to a photosensitive film) on the seed layer on the surface of the glass substrate 111, and exposing and developing the photoresist layer to form a patterned photoresist layer 113 (equivalent to a second patterned window) (see paragraph [0069] of the specification, fig. 1c); Forming a conductive material layer 114 in the through hole 111c (equivalent to making a second rewiring layer in the patterned window and filling a copper column connected with the second rewiring layer in the through hole) (see paragraph [0070] of the specification, fig. 1d); The conductive material layer 114 may be copper. Remove the residual photoresist layer and flash etch the exposed seed layer (see paragraph [0071] in the specification, Figure 1E)”.
Therefore, it is obvious to the technical personnel in this field that other parallel technical solutions claimed in this claim are obtained on the basis of reference Yang as modified by Tao, Tang and Zeng and common technical means in this field. Therefore, the other parallel technical solutions claimed in this claim do not have outstanding substantive features and significant progress, so they do not have creativity”.
In regard to claim 18, Yang (Abstract, paragraphs 26-34, Fig. 1 and associated text) as modified by Tao does not specifically disclose wherein a method of preparing the glass metallized circuit structure comprises following steps: S100: providing a second glass substrate, and carrying out laser modification on a portion of the second glass substrate; S200: etching the second glass substrate to form a through hole in a laser-modified region; S300: preparing a seed layer on an inner wall of the through hole and both surfaces of the second glass substrate; S400: separately pressing a photosensitive film onto the seed layer on the both surfaces of the second glass substrate, and carrying out exposure and development to form a patterned window; S500: preparing a second redistribution layer in the patterned window, and filling in the through hole a copper pillar connected to the second redistribution layer; S600: removing a residual photosensitive film, and carrying out flash etching on an exposed seed layer; S700: preparing a solder mask on one side of the second glass substrate and a surface of a second redistribution layer corresponding to the one side of the second glass substrate to cover the one side of the second glass substrate and the second redistribution layer; S800: preparing (m+1) first substrate structures according to steps S100-S700, wherein m is a positive integer, carrying out hole opening on a solder mask of each of m first substrate structures to expose a pad region of a second redistribution layer of each of the m first substrate structures, and implanting a metal bump in the pad region to obtain a second substrate structure serving as an intermediate; and S900: coating a metal bump of one second substrate structure with a nanometal paste, and butt-joining and securing by sintering the metal bump of the one second substrate structure to an exposed second redistribution layer of a first substrate structure; then, coating a metal bump of another second substrate structure with the nanometal paste, and butt-joining and securing by sintering the metal bump of the another second substrate structure to an exposed second redistribution layer of the one second substrate structure; securing all second substrate structures in a same manner; finally, filling the connecting material between the first substrate structure and the second substrate structure and between each of two adjacent second substrate structures, and carrying out sintering on the connecting material to obtain the glass metallized circuit structure.
Tang (see paragraphs [0066]- [0093] in the specification, and Figures 1-6) “discloses that, as can be seen from Figure 1-2, a glass substrate 101 (equivalent to a second glass substrate) is provided; By laser-induced etching, electrochemical method, laser ablation method, plasma etching method, focused discharge method, photosensitive glass method, sand blasting method, etc. An interconnection hole 102 (equivalent to a through hole) is formed. It can be seen that reference document 5 discloses the preparation of through holes in the glass substrate by laser-induced etching. The laser-induced etching method usually includes modifying the region of the glass substrate where the through hole is to be formed by laser to form a laser- modified region, and then forming the through hole in the laser-modified region by etching, which is a common technical means in this field. On the basis of reference document 5, it is easy to obtain by combining with common technical means in this field, such as the technical scheme of laser modifying part of the second glass substrate and forming a through hole in the laser modified area. In order to protect the rewiring layer and the surface of the glass substrate, technicians in this field usually prepare solder resist layers covering the second glass substrate and the second rewiring layer on one side of the second glass substrate and the corresponding surface. This is a common technical means in this field, which has not brought
unexpected technical effects. However, the number of first substrate structures can be designed by technicians in the field according to actual needs, such as making m+1 first substrate structures, where m is positive. Integer, which is a common technical means in this field, has not brought unexpected technical effects. In order to stack the m first substrate structures on the m+1th first substrate structure, the technicians in the field usually open holes in the solder resist layer of the m first substrate structures to expose the pad area of the second rewiring layer of the first substrate structure, and implant metal bumps in the pad area to manufacture the second substrate structure which can be used as an intermediate. One of the metal bumps of the second substrate structure is coated with nano-metal paste and then bonded with the exposed second rewiring layer of the first substrate structure, and then sintered and fixed; the other metal bump of the second substrate structure is coated with nano-metal paste and bonded with the exposed second rewiring layer of the second substrate structure, and all the second substrate structures are fixed by analogy; and finally, the connecting material is filled between the first substrate structure and the second substrate structure and every two adjacent second substrate structures and sintered to obtain the glass metallized circuit structure”.
Zeng discloses a method for preparing a glass metallized circuit structure (see paragraphs [0066]-[0071] in the specification, and Figures 1A- 1E): providing a glass substrate 111 (equivalent to the second glass substrate) (see Figure 1a); A through hole 111c (see fig. 1A) is formed by, for example, drilling the glass substrate 111 by laser; Forming a seed layer 112 on the inner wall of the through hole 111c and the first surface 111a and the second surface 111b of the glass substrate 111 (see fig. 1b); Calendering a resist layer (equivalent to a photosensitive film) on the seed layer on the surface of the glass substrate 111, and exposing and developing the photoresist layer to form a patterned photoresist layer 113 (equivalent to a second patterned window) (see paragraph [0069] of the specification, fig. 1c); A conductive material layer 114 is
formed in the through hole 111c. (It is equivalent to making the second rewiring layer in the patterned window and filling the copper column connected with the second rewiring layer in the through hole) (see paragraph [0070] of the specification, figure 1d); The conductive material layer 114 may be copper. Remove the residual photoresist layer and flash etch the exposed seed layer (see paragraph [0071] in the specification, Figure 1E).
Therefore, it is obvious to the technical personnel in this field that other parallel technical solutions claimed in this claim are obtained on the basis of Yang as modified by Tao, Tang and Zeng and common technical means in this field. Therefore, the other parallel technical solutions claimed in this claim do not have outstanding substantive features and significant progress, so they do not have creativity.
Conclusion
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TELLY D. GREEN
Examiner
Art Unit 2898
/TELLY D GREEN/Primary Examiner, Art Unit 2898 August 25, 2026
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