DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the limitation of “the trench also has the sintered metal layer in the trench formed on the outside of the semiconductor chip mounting region” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1- 9 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Gai (U.S. 2005/0046008 A1, hereinafter refer to Gai) in view of Tatsumi et al. (U.S. 2018/0190611 A1, hereinafter refer to Tatsumi).
Regarding Claim 1: Gai discloses a semiconductor device (see Gai, Fig.3 as shown below and ¶ [0002]), comprising:
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a wiring layer (212) (see Gai, Fig.3 as shown above),
a semiconductor chip (220) (see Gai, Fig.3 as shown above), and
a sintered metal layer (130 or 230/ adhesive, such as silver paste) that bonds the semiconductor chip (220) to the wiring layer (212) (see Gai, Fig.3 as shown above and ¶ [0005]),
wherein: the wiring layer (212) has a trench (212e/212d) extending from a semiconductor chip mounting region in which the semiconductor chip (220) is mounted to an outside of the semiconductor chip mounting region (see Gai, Fig.3 as shown above),
the trench (212e/212d) has, in the semiconductor chip mounting region, the sintered metal layer (130 or 230/ adhesive, such as silver paste) formed in the trench (212d/212e) and on an outside of an upper end of the trench (212d) (see Gai, Fig.3 as shown above),
the trench (212d/212e) also has the sintered metal layer (130 or 230/ adhesive, such as silver paste) in the trench (212d) formed on the outside of the semiconductor chip mounting region (see Gai, Fig.3 as shown above), and
the trench (212d/212e) is different in depth between a vicinity of a center of the semiconductor chip mounting region and a vicinity of an end portion of the semiconductor chip mounting region (see Gai, Fig.3 as shown above).
Gai is silent upon explicitly disclosing wherein the adhesive, such as silver paste is a sintered metal layer.
For support see Tatsumi, which teaches wherein the adhesive, such as silver paste is a sintered metal layer (see Tatsumi, Fig.1 and ¶ [0040]- ¶ [0041]).
Thus, it would have been within the scope of one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Gai and Tatsumi to enable the known sintering process for forming the silver paste adhesive layer of Gai’s according to the teachings of Tatsumi because one of ordinary skill in the art before effective filing date of the claimed invention would have been motivated to look to alternative suitable methods of performing the disclosed silver paste adhesive layer of Gai and art recognized suitability for an intended purpose has been recognized to be motivation to combine. MPEP § 2144.07.
Note: patentability of a product does not depend on its method of production.
Regarding Claim 2: Gai as modified teaches a semiconductor device as set forth in claim 1 as above. The combination of Gai and Tatsumi further teaches wherein: a depth of the trench (212d/212e) different between the vicinity of the center of the semiconductor chip mounting region and the vicinity of the end portion of the semiconductor chip mounting region is deeper in the vicinity of the center of the semiconductor chip mounting region and is shallower in the vicinity of the end portion of the semiconductor chip mounting region (see Gai, Fig.3 as shown above).
Regarding Claim 3: Gai as modified teaches a semiconductor device as set forth in claim 2 as above. The combination of Gai and Tatsumi further teaches wherein: a width of the trench (212d/212e) different between the vicinity of the center of the semiconductor chip mounting region and the vicinity of the end portion of the semiconductor chip mounting region is narrower in the vicinity of the center of the semiconductor chip mounting region and is wider in the vicinity of the end portion of the semiconductor chip mounting region (see Gai, Fig.3 as shown above).
Regarding Claim 4: Gai as modified teaches a semiconductor device as set forth in claim 1 as above. The combination of Gai and Tatsumi further teaches wherein: the trench (212d/212e) has an inclined surface at an upper end thereof in the vicinity of the semiconductor chip (220) (see Gai, Fig.3 as shown above).
Regarding Claim 5: Gai as modified teaches a semiconductor device as set forth in claim 1 as above. The combination of Gai and Tatsumi further teaches wherein: the trench (212d/212e) includes a plurality of trenches (see Gai, Fig.3 as shown above and Figs.4-5),
the plurality of trenches (212d/212e3) extends in parallel to each other in a first direction (see Gai, Fig.3 as shown above and Figs.4-5), and
each of the plurality of trenches extends in a second direction intersecting the first direction (see Gai, Fig.3 as shown above and Figs.4-5).
Regarding Claim 6: Gai as modified teaches a semiconductor device as set forth in claim 5 as above. The combination of Gai and Tatsumi further teaches wherein: in the first direction, the depth of each of the plurality of trenches (212d/212e) is deepest in the vicinity of the center and the depth gradually decreases from the vicinity of the center to the vicinity of the end portion (see Gai, Fig.3 as shown above).
Regarding Claim 7: Gai as modified teaches a semiconductor device as set forth in claim 6 as above. The combination of Gai and Tatsumi further teaches wherein: in the second direction, the depth of each of the plurality of trenches (212d/212e) is deepest in the vicinity of the center and the depth gradually decreases from the vicinity of the center to the outside of the semiconductor chip mounting region (see Gai, Fig.3 as shown above).
Regarding Claim 8: Gai as modified teaches a semiconductor device as set forth in claim 7 as above. The combination of Gai and Tatsumi further teaches wherein: the plurality of trenches (212e) has the same width in the first direction (see Gai, Fig.3 as shown above).
Regarding Claim 9: Gai as modified teaches a semiconductor device as set forth in claim 7 as above. The combination of Gai and Tatsumi further teaches wherein: with regards to the width (212d/212e) of each of the plurality of trenches, the width in the vicinity of the center is the narrowest and the width gradually increases from the vicinity of the center to the vicinity of the end portion (see Gai, Fig.3 as shown above).
Regarding Claim 11: Gai as modified teaches a semiconductor device as set forth in claim 1 as above. The combination of Gai and Tatsumi further teaches electric power conversion device, comprising the semiconductor device as claimed in Claim 1, wherein: the semiconductor chip is an IGBT or MOSFET power transistor or a diode (see Gai, Fig.3 as shown above).
Claim(s) 10 is rejected under 35 U.S.C. 103 as being unpatentable over Gai (U.S. 2005/0046008 A1, hereinafter refer to Gai) and Tatsumi et al. (U.S. 2018/0190611 A1, hereinafter refer to Tatsumi) as applied to claim 7 above, and further in view of Dreher et al. (EP 3940769 A1, hereinafter refer to Dreher).
Regarding Claim 10: Gai as modified teaches a semiconductor device as applied to claim 7 above. The combination of Gai and Tatsumi is silent upon explicitly disclosing wherein: each of the plurality of trenches has, at an upper end thereof, an inclined surface in the vicinity of the semiconductor chip.
For support see Dreher, which teaches wherein: each of the plurality of trenches (34) has, at an upper end thereof, an inclined surface in the vicinity of the semiconductor chip (4) (see Dreher, Figs.1 and 11 as shown below and abstract).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Gai, Tatsumi, and Dreher to enable each of the plurality of trenches to have, at an upper end thereof, an inclined surface in the vicinity of the semiconductor chip as taught by Dreher in order to obtain a semiconductor module which has improved heat dissipation and greater reliability.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BITEW A DINKE whose telephone number is (571)272-0534. The examiner can normally be reached M-F 7 a.m. - 5 p.m..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571)272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BITEW A DINKE/Primary Examiner, Art Unit 2812
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