DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 13 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chung (KR 20090088670 A).
Regarding claim 13, Chung teaches a method for manufacturing a semiconductor device (Figs. 8a-8d and corresponding text), the method comprising:
forming a gate electrode on a first semiconductor layer including a first semiconductor material through an insulating film (Fig. 8a, 700/702/704),
forming a drain region by replacing a part of the first semiconductor layer adjacent to a region where the gate electrode is formed with a second semiconductor material having a band gap wider than a band gap of the first semiconductor material (Figs. 8b-8c, 710 has larger bandgap);
forming a source region in the first semiconductor layer adjacent to the region where the gate electrode is formed (Fig. 8d, 712a).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-7 are rejected under 35 U.S.C. 103 as being unpatentable over Chung (KR 20090088670 A) in view of Oxland (U.S PGPub 2016/0149001).
Regarding claim 1, Chung teaches a semiconductor device (Fig. 8d), comprising:
a source region of a first conductivity type which includes a first semiconductor material, a channel region of a second conductivity type which is adjacent to the source region and includes the first semiconductor material 28, [0020]), a first drain region which is adjacent to the channel region and including a second semiconductor material having a band gap wider than a band gap of the first semiconductor material; and a second drain region of the first conductivity type that is adjacent to the first drain region and includes the second semiconductor material (Fig. 8 and corresponding text; source 712a, second drain region 712b, first semiconductor material 700, second semiconductor material 710 with larger bandgap; source and drain regions by definition have the same conductivity type).
Chung does not explicitly teach wherein the first drain region is of the second conductivity type.
Oxland teaches a transistor having a drain region with wider band gap (Fig. 4, 22, [0037]), comprising a first and second drain region, where the first drain region is adjacent to the channel region and has the same conductivity type and the second drain region has the opposite conductivity type, the same as the source region (Fig. 7, [0040]-[0042]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Oxland with Chung such that the first drain region is of the second conductivity type for the purpose of choosing appropriate doping for the channel region (Oxland, [0041]).
Regarding claim 2, the combination of Chung and Oxland teaches wherein the first semiconductor material is Si, and the second semiconductor material is SiC, GaN, AlN, InN, GaAs, diamond, ZnO, or AlGaN (semiconductor substrate 700 is Si; semiconductor layer 710 may be SiC or GaN). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Chung and Oxland for the reasons set forth in the rejection of claim 1.
Regarding claim 3, the combination of Chung and Oxland teaches wherein the first conductivity type is one of an N-type and a P-type, and the second conductivity type is the other of an N-type and a P-type different from the first conductivity type (Oxland, [0040]-[0041]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Chung and Oxland for the reasons set forth in the rejection of claim 1.
Regarding claim 4, the combination of Chung and Oxland teaches wherein the source region, the channel region, the first drain region, and the second drain region are provided adjacent to each other in an in-plane direction of a first semiconductor layer including the first semiconductor material (Chung, Fig. 8D). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Chung and Oxland for the reasons set forth in the rejection of claim 1.
Regarding claim 5, the combination of Chung and Oxland teaches wherein the first drain region and the second drain region are provided in a region in which a part of the first semiconductor layer is replaced with the second semiconductor material (Chung, Fig. 5D). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Chung and Oxland for the reasons set forth in the rejection of claim 1.
Regarding claim 6, the combination of Chung and Oxland teaches wherein the second drain region is provided inside the first drain region (Chung, Fig. 5D). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Chung and Oxland for the reasons set forth in the rejection of claim 1.
Regarding claim 7, the combination of Chung and Oxland teaches a gate electrode adjacent to the channel region through an insulating film (Chung, 702/704). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Chung and Oxland for the reasons set forth in the rejection of claim 1.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Chung (KR 20090088670 A) in view of Oxland (U.S PGPub 2016/0149001) and Kim (U.S. PGPub 2023/0075559).
Regarding claim 8, the combination of Chung and Oxland does not explicitly teach wherein the first semiconductor layer is provided in a fin shape, and the gate electrode is adjacent to the channel region by two or more surfaces.
Kim teaches wherein a transistor having a source/drain region with a modified bandgap may be formed as a planar transistor, a recessed gate transistor, a finFET, or a gate-all-around transistor (Figs. 1-17, [0039]-[0049]).
Therefore it would have been obvious to a person having ordinary skill in the art to combine the teachings of Kim with Chung and Oxland such that the first semiconductor layer is provided in a fin shape, and the gate electrode is adjacent to the channel region by two or more surfaces for the purpose of providing the GIDL reduction of Chung to a finFET transistor because the alternative structures provided in Kim would provide a reasonable expectation of success.
Claims 9 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Chung (KR 20090088670 A) in view of Oxland (U.S PGPub 2016/0149001) and Disney (U.S. PGPub 2008/0085603).
Regarding claims 9 and 11, the combination of Chung and Oxland does not explicitly teach wherein the source region, the channel region, the first drain region, and the second drain region are provided adjacent to each other in a thickness direction of a second semiconductor layer including the second semiconductor material, and wherein the gate electrode is adjacent to the channel region through an insulating film.
Disney teaches a vertical transistor device wherein a gate electrode is embedded in a second semiconductor layer comprising the drain region (Fig. 1I, 11/12, [0015]-[0016], gate electrode 33a/b embedded in trenches formed in layer 12, [0023]-[0024], trench gate), wherein the source region, channel region, and drain region are provided adjacent to each other in a thickness direction of the second semiconductor layer (Fig. 1I, 38/39/12, [0026]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Chung and Oxland such that the source region, the channel region, the first drain region, and the second drain region are provided adjacent to each other in a thickness direction of a second semiconductor layer including the second semiconductor material, and wherein the gate electrode is adjacent to the channel region through an insulating film for the purpose of providing the GIDL reduction of Chung to an HVFET (Disney, [0026]).
Allowable Subject Matter
Claim 10 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 10, the prior art, alone or in combination, does not explicitly teach wherein the source region and the channel region are provided in a region where a part of the second semiconductor layer is replaced with the first semiconductor material in combination with the other limitations. Cheng (U.S. PGPub 2019/0341488) teaches replacing the source region but not the source and channel region, and the source, channel, and multiple drain regions are not embedded in the second semiconductor layer.
Conclusion
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/ALIA SABUR/Primary Examiner, Art Unit 2812
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