DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Masaki et al (JP 2008004866A).
With respect to Claim 1, Masaki et al discloses a semiconductor device as an RC-IGBT (Figures 2 and 7) having an IGBT part ( Figure 7, 14) and a diode part (Figure 7, 1) in a single chip, wherein a body of the diode part is formed shallower than a body layer of the IGBT part (Figure 7), a lifetime control layer (Figures 2 and 7, 4) of the IGBT part (Figure 7, 14) is formed in the body layer of the IGBT part, and
the lifetime control layer (Figures 2 and 7, 4) of the diode part (Figure 7, 1) is formed in a drift layer (Figure 7, N-) below the body part of the diode part (Figure 7, 1). See Figures 2 and 7 and corresponding text, especially paragraphs 23-39.
With respect to Claim 2, Masaki et al disclose wherein the semiconductor device according to claim 1, wherein the lifetime control layer (Figures 2 and 7, 4) of the IGBT part (Figure 7, 14) and the lifetime control layer (Figures 2 and 7, 4) of the diode part (Figure 7, 1) are formed at the same depth. See Figures 2 and 7 and corresponding text.
With respect to Claim 3, Masaki et al disclose wherein the lifetime control layer is made of light ion. See Figure 2A, paragraph 23 (boron).
With respect to Claim 4, Masaki et al disclose wherein the body layer of the IGBT part and the body layer of the diode part are formed in different steps. See Figures 2-6 and corresponding text.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Masaki et al (JP 2008004866A) in view of Arai et al (US 2017/0317075).
Masaki et al is relied upon as discussed above.
However, Masaki et al does not disclose an electric power converter comprising : a pair of DC terminals; AC terminals of the number which is equal to the number of phases of AC output; switching legs of the number which is equal to the number of phases of AC output, the switching legs being connected between the pair of DC terminals, and the switching leg including two parallel circuits connected in series, and each of the two parallel circuits being formed of a switching element and a diode connected reversely in parallel to the switching elements; and a gate circuit controlling the switching element, wherein the diode and the switching element are the semiconductor device of Claim 1.
Arai et al discloses an electric power converter (Figure 12) comprising : a pair of DC terminals (Figure 12, 911, 912) ; AC terminals of the number which is equal to the number of phases of AC output (Figure 12) ; switching legs of the number which is equal to the number of phases of AC output, the switching legs being connected between the pair of DC terminals, and the switching leg including two parallel circuits connected in series (paragraphs 170-179 and 207) , and each of the two parallel circuits being formed of a switching element and a diode connected reversely in parallel to the switching elements; and a gate circuit (Figure 12, 801-806) controlling the switching element. See Figure 12 and corresponding text, especially paragraphs 50-57, 170-179 and 207).
It would have been obvious for one of ordinary skill in the art, before the effective date of the invention, to use the semiconductor device of Masaki et al in the electric power converter of Arai et al, for its known benefit in the art as a diode and switching element. The use of a known device, for its known benefit, would have been prima facie obvious to one of ordinary skill in the art.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER G GHYKA whose telephone number is (571)272-1669. The examiner can normally be reached Monday-Friday 9-6.
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AGG
August 30, 2026
/ALEXANDER G GHYKA/Primary Examiner, Art Unit 2812
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