DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
Figures 1 – 7 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 7, 9, 11, and 14 – 20 are rejected under 35 U.S.C. 103 as being unpatentable over Higashi et al. (US 2016/0088243) in view of Shimizu et al. (US 2021/0273002).
Regarding claim 1, Higashi teaches (FIG. 24 – 28):
A semiconductor device comprising a stack of a first semiconductor substrate (30B) and a second semiconductor substrate (30A), wherein the first semiconductor substrate includes:
an imaging element (PD1) that generates a charge in response to light from a light incident surface of the first semiconductor substrate; and
a first memory element (VR1, MRAM, [0089] – [0099])
Higashi fails to expressly disclose the MRAM structure:
provided on a side opposite to the light incident surface with respect to the imaging element, and the first memory element has a stacked structure in which a magnetization fixed layer, a nonmagnetic layer, and a storage layer are stacked in the order mentioned from the light incident surface side.
However, Shimizu teaches (FIG. 2, [0017] – [0027]) memory element (24) and memory element (56) is formed in a layered order on the light incident surface side.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to apply the layering structure of the MRAM device of Shimizu in the MRAM element of Higashi for the further advantage of enabling a magnetic memory element integrated with an imaging structure in a conventional manner.
Regarding claim 2, Shimizu teaches (FIG. 2):
The semiconductor device according to claim 1, wherein a cross section of the first memory element cut along a stacking direction has a trapezoidal shape, and a length of an upper base located on the light incident surface side of the trapezoid is longer than a length of a lower base of the trapezoid.
Regarding claim 3, Higashi teaches (FIG. 24):
The semiconductor device according to claim 1, wherein the second semiconductor substrate includes a logic circuit (17).
Regarding claim 4, Shimizu teaches (FIG. 7):
The semiconductor device according to claim 1, wherein the first semiconductor substrate and the second semiconductor substrate are joined to each other by junction electrodes (48, 54) provided to the first semiconductor substrate and the second semiconductor substrate.
Regarding claim 5, Shimizu teaches:
The semiconductor device according to claim 4, wherein the junction electrodes are formed of copper ([0043]).
Regarding claim 6, Shimizu teaches (FIG. 2):
The semiconductor device according to claim 1, wherein the first memory element further includes a first electrode and a second electrode sandwiching the stacked structure, the first electrode is located on the light incident surface side with respect to the stacked structure, and the second electrode is electrically connected with a selection transistor (20Tr).
Regarding claim 7, Higashi teaches (FIG. 27):
The semiconductor device according to claim 6, wherein the selection transistor is an n-type MOS transistor.
Regarding claim 9, Higashi teaches (FIG. 26, 28):
The semiconductor device according to claim 1, wherein the first semiconductor substrate includes: a pixel region including a plurality of the imaging elements arrayed two-dimensionally; and a memory area including a plurality of the first memory elements arrayed two-dimensionally.
Regarding claim 11, Higashi teaches:
The semiconductor device according to claim 9, wherein at least some of the plurality of first memory elements are nonvolatile storage elements (MRAM [0099]).
Regarding claim 14, Higashi teaches:
The semiconductor device according to claim 9, wherein the memory area includes a logic circuit (14, FIG. 24).
Regarding claim 15, Higashi fails to expressly disclose:
The semiconductor device according to claim 1, wherein the second semiconductor substrate does not include a memory element.
However, it would have been an obvious matter of design choice to one having ordinary skill in the art before the effective filing date of the claimed invention to provide the necessary variable resistance memory structures in whichever substrate was necessary or expedient to achieve the desired final design.
Regarding claim 16, Higashi teaches series variable resistance elements ([0170] – [0176]):
The semiconductor device according to claim 9, wherein the second semiconductor substrate includes a plurality of second memory elements.
Regarding claim 17, Shimizu teaches ([0010] – [0027]):
The semiconductor device according to claim 16, wherein each of the second memory elements has a stacked structure in which a storage layer, a nonmagnetic layer, and a magnetization fixed layer are stacked in the order mentioned from the first semiconductor substrate side.
Regarding claim 18, Higashi teaches series variable resistance elements ([0170] – [0176]):
The semiconductor device according to claim 16, wherein each of the first memory elements and each of the second memory elements are connected in series.
Regarding claim 19, Higashi teaches series variable resistance elements ([0170] – [0176]):
The semiconductor device according to claim 18, further comprising a plurality of memory element pairs each including one of the first memory elements and one of the second memory elements connected in series, wherein individual resistance values of the plurality of memory element pairs are different from each other.
Regarding claim 20, Higashi teaches (FIG. 24 – 28):
An electronic device (FIG. 12) mounted with a semiconductor device, the semiconductor device including a stack of a first semiconductor substrate (30B) and a second semiconductor substrate (30A), wherein the first semiconductor substrate includes:
an imaging element (PD1) that generates a charge in response to light from a light incident surface of the first semiconductor substrate; and
a first memory element (VR1)
Higashi fails to expressly disclose the MRAM structure:
provided on a side opposite to the light incident surface with respect to the imaging element, and the first memory element has a stacked structure in which a magnetization fixed layer, a nonmagnetic layer, and a storage layer are stacked in the order mentioned from the light incident surface side.
However, Shimizu teaches (FIG. 2, [0017] – [0027]) memory element (24) and memory element (56) is formed in a layered order on the light incident surface side.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to apply the layering structure of the MRAM device of Shimizu in the MRAM element of Higashi for the further advantage of enabling a magnetic memory element integrated with an imaging structure in a conventional manner.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Higashi et al. (US 2016/0088243) in view of Shimizu et al. (US 2021/0273002) as applied to claim 9 above, and further in view of Yokoyama et al. (US 2018/0025765).
Regarding claim 10, Higashi fails to expressly disclose:
The semiconductor device according to claim 9, wherein at least some of the plurality of first memory elements are volatile storage elements.
However, Yokoyama teaches a memory element comprising volatile (10) and non-volatile (20) memory structures.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to implement the memory configuration of Yokoyama in the structure of Higashi for the predictable advantage of improving operational speed and lower power consumption of the memory structure in a conventional manner.
Regarding claim 12, Higashi fails to expressly disclose:
The semiconductor device according to claim 9, wherein the plurality of first memory elements includes a volatile storage element and a nonvolatile storage element.
However, Yokoyama teaches a memory element comprising volatile (10) and non-volatile (20) memory structures.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to implement the memory configuration of Yokoyama in the structure of Higashi for the predictable advantage of improving operational speed and lower power consumption of the memory structure in a conventional manner.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Higashi et al. (US 2016/0088243) in view of Shimizu et al. (US 2021/0273002) as applied to claim 9 above, and further in view of Perner et al. (US 6,324,093).
Regarding claim 13, Higashi teaches various resistive memory structures, but fails to expressly disclose:
The semiconductor device according to claim 11, wherein the nonvolatile storage element includes an OTP storage element in which the nonmagnetic layer is destroyed.
However, Perner teaches magnetic one-time programmable memory structures (FIG. 2) wherein a non-magnetic layer (36) breaks down.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to apply the OTP teachings of Perner to the device of Higashi for the predictable advantage of enabling permanent programming of a resistive magnetic memory device in a conventional manner.
Allowable Subject Matter
Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art of record fails to teach or fairly render obvious wherein the first memory element is electrically connected to a read transistor and a write transistor, and film thicknesses of gate oxide films of the read transistor and the write transistor are different from each other, in combination with the other limitations of the claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CORY W ESKRIDGE whose telephone number is (571)272-0543. The examiner can normally be reached M - F 9 - 5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Madonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CORY W ESKRIDGE/Primary Examiner, Art Unit 2898
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