DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-11, 15 and 16 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Hwangbo et al. (US20170373108A1).
Regarding claim 1, Figs.5A and 5B of Hwangbo teach a solid-state imaging device comprising: a trench Td (para.0062) that isolates a pixel Px (Fig.3B, para.0053); and a pixel transistor (para.0057) that forms a channel region CH (para.0063) along a side surface of the trench Td in a direction intersecting a depth direction of the trench Td (wherein the channel has a structure that extends in x, y and z direction (i.e., the channel is a 3D structure) and thus (as depicted in Fig.3B) the channel region intersects the depth direction of the trench in view of x and z direction, where y is the depth direction of the trench).
Regarding claim 2, Hwangbo further teaches the solid-state imaging device according to claim 1, wherein at least a part of a gate electrode 43 (para.0059) of the pixel transistor is located in the trench Td (para.0062).
Regarding claim 3, Hwangbo further teaches the solid-state imaging device according to claim 1, wherein the direction intersecting the depth direction of the trench Td (Fig.5B, para.0062) includes at least one of a column direction or a row direction.
Regarding claim 4, Hwangbo further teaches the solid-state imaging device according to claim 1, wherein the pixel transistor includes at least one of a drive transistor, a selection transistor, a reset transistor, or a transfer transistor (para.0057).
Regarding claim 5, Hwangbo further teaches the solid-state imaging device according to claim 1, wherein at least one of a source, a drain, or a floating diffusion FD (para.0059) of the pixel transistor is located on the side surface of the trench Td (para.0062).
Regarding claim 6, Hwangbo further teaches the solid-state imaging device according to claim 1, further comprising: an insulating layer 45 (para.0067) embedded in a part of the trench Td (para.0067) in the depth direction, wherein a part of a gate electrode 43 (para.0067) of the pixel transistor is located on the side surface of the trench Td on the insulating layer 45 with a gate insulating film 41 (para.0062) interposed between the part of the gate electrode 43 and the side surface.
Regarding claim 7, Hwangbo further teaches the solid-state imaging device according to claim 1, wherein a part of a gate electrode 43 (para.0067) of the pixel transistor is located on the pixel Px (Fig.2A, para.0053).
Regarding claim 8, Fig.3B of Hwangbo further teaches the solid-state imaging device according to claim 7, further comprising a spacer insulating layer 50 (para.0062) located below the gate electrode 43 (para.0062) of the pixel transistor on the pixel Px (para.0061).
Regarding claim 9, Hwangbo further teaches the solid-state imaging device according to claim 1, wherein at least one of sources, drains (para.0058), or floating diffusions FD (para.0059) of adjacent pixels are isolated from each other by the trench Td (para.0062).
Regarding claim 10, Hwangbo further teaches the solid-state imaging device according to claim 1, further comprising: a contact plug (para.0058) connected to each of sources, drains (para.0058), and floating diffusions FD (para.0059) of adjacent pixels isolated from each other by the trench Td (para.0062); and a wiring line 60 (para.0061) that connects the sources, the drains, and the floating diffusions FD each other which are isolated by the trench Td, via the contact plug (para.0058) connected to each of the sources, the drains, and the floating diffusions FD isolated by the trench Td.
Regarding claim 11, Hwangbo further teaches the solid-state imaging device according to claim 1, further comprising a contact plug (para.0058) connected across the trench Td (para.0062) to each of sources, drains, and floating diffusions isolated from each other by the trench Td between adjacent pixels Px (Fig.2B, para.0053).
Regarding claim 15, Hwangbo further teaches the solid-state imaging device according to claim 1, wherein a transfer transistor used as the pixel transistor has a planar structure (see Fig.2B, para.0057), and an end in a width direction of a gate electrode 43 (para.0067) of the transfer transistor is located on an insulating layer 45 (para.0067) embedded in the trench Td (para.0067).
Regarding claim 16, Hwangbo further teaches the solid-state imaging device according to claim 1, wherein an end in a width direction of a gate electrode 43 (para.0067) of a transfer transistor used as the pixel transistor is located on the side surface of the trench Td (para.0062).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Hwangbo et al. (US20170373108A1) in view of Nakata et al. (US20100230583A1).
Regarding claim 12, Hwangbo does not teach wherein the solid-state imaging device according to claim 1, further comprising a base layer that is connected across the trench to each of sources, drains, and floating diffusions isolated from each other by the trench between adjacent pixels, and includes the same material as a material of a gate electrode of the pixel transistor.
Fig.45 of Nakata teaches a solid state image pickup device that includes a base layer that is formed in a group of a plurality of pixels at a position below a light incidence surface of the group and has layouts including electrodes and wirings. The base layer may be a base layer including a gate electrode and a wiring portion of the pixel transistor. (para.0020-0021). Fig.48 of Nakata teaches wherein in the unit pixel group 114, a base layer including gate electrodes made of polysilicon has an asymmetrical arrangement with respect to the boundary of adjacent pixels (para.0227).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Nakata’s base layer and gate electrode, that is made of polysilicon, in the teachings of Hwangbo because base layer made of polysilicon serves as adjusting means for obtaining optical symmetry (Nakata, [para.0313]).
Regarding claim 13, the combination of Hwangbo and Nakata further teaches the solid-state imaging device according to claim 12, wherein a part of the base layer connected to each of the sources 7 (Nakata, para.0014) and the drains 8 (Nakata, para.0014) is located in the trench.
Regarding claim 14, Nakata further teaches the solid-state imaging device according to claim 12, wherein the materials of the gate electrode 43/48/49/151 (para.0235) of the pixel transistor and the base layer (para.0227) include polycrystalline silicon into which impurities are introduced.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINCENT KIPKEMOI RONO whose telephone number is (571)270-5977. The examiner can normally be reached Mon-Fri, 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571)272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
VINCENT KIPKEMOI. RONO
Examiner
Art Unit 2891
/V.K.R./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
Prosecution Insights