DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Status of the application
This office Action is in response to Applicant's Application filled on 09/09/2024. Claims 1-18 are cancelled and 19-38 are pending for this examination.
Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d). The certified copy has been filed on 09/09/2024.
Oath/Declaration
The oath or declaration filed on 09/09/2024 is acceptable.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 19-38 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as failing to set forth the subject matter which the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the applicant regards as the invention.
Regarding Claim 19, The instant claims recite limitation “wherein the layer is grown leaving multiple thicker grown islands connected via thinner sections of the first layer” is not clear because the layer is referred to first layer or different layer, is not defined. In addition, “the final grown material,” appears lacks proper antecedent. Therefore, the resulting claim is indefinite and is failing to particularly point out and distinctly claim the subject matter. Appropriate corrections defining these limitations within metes and bounds of the claimed invention are required.
Regarding Claim 20, The instant claims recite limitation “the third layer having a thickness within an approximate range of 1-100nm, wherein y is within a range of 0-0.9, z is within a range of 0-1.0, is less than (y + 1),z decreases in an interval from the area close to the second layer” is not clear because an interval from the area is not defined. Therefore, the resulting claim is indefinite and is failing to particularly point out and distinctly claim the subject matter. Appropriate corrections defining these limitations within metes and bounds of the claimed invention are required.
Regarding Claim 23, The instant claims recite limitation “wherein the first layer is added with phosphorus in step (ii), thereby providing a material with a lattice constant in between 5.463A (AIP) and 6.136A (AISb)” is not clear because 5.463A (AIP) is not defined claim 20. In addition, a lattice constant between 5.463A (AIP) and 6.136A (AISb) is based on any III-V material, is not defined. Therefore, the resulting claim is indefinite and is failing to particularly point out and distinctly claim the subject matter. Appropriate corrections defining these limitations within metes and bounds of the claimed invention are required.
Regarding Claim 27, The instant claims recite limitation “wherein the second layer is added with phosphorus in step (iii), thereby providing a material having a lattice constant between 5.451A (GaP) and 6.479A (InSb)” is not clear because 6.479A (InSb) is not defined claim 24. In addition, lattice constant between 5.451A (GaP) and 6.479A (InSb) is based on any III-V material, is not defined. Therefore, the resulting claim is indefinite and is failing to particularly point out and distinctly claim the subject matter. Appropriate corrections defining these limitations within metes and bounds of the claimed invention are required.
Regarding Claim 37, The instant claims recite limitation “wherein the steps (i)-(iii) for manufacturing the semiconductor material are performed by moving the silicon substrate through several evaporation zones with different deposition methods” is not clear because claim 35 discloses “wherein the steps (i)-(iii) for manufacturing the semiconductor material are performed in a Molecular Beam Epitaxy machine”, therefore, how substrate through several evaporation zones with different deposition methods is unclear. Therefore, the resulting claim is indefinite and is failing to particularly point out and distinctly claim the subject matter. Appropriate corrections defining these limitations within metes and bounds of the claimed invention are required.
Claims 20-38 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, because of their dependency status from claim 19.
Claim Rejection- 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 19, 28, 31 and 34-36 are rejected under 35 U.S.C. 103 as being unpatentable over Chua et al (US 2009/0001416 A1; hereafter Chua) in view of Vielemeyer et al (US 2011/0049681 A1; hereafter Vielemeyer).
PNG
media_image1.png
360
607
media_image1.png
Greyscale
Regarding claim 19. Chua discloses a method of manufacturing a semiconductor material (Fig. [5]), comprising the steps of:
(i) providing a silicon substrate (Fig 5, substrate 10 which can be sapphire, silicon or other suitable substrates, Para [ 0026]) having a thickness within an approximate range of 40-1000µm (Para [ 0026]) and
(ii) growing a first layer (buffer layer 16, Para [0028]) comprising III-V materials on top of the silicon substrate (Fig 5, substrate 10), the first layer (buffer layer 16, Para [ 0028]) having a thickness within an approximate range of 1-100nm (buffer layer 16, Para [ 0028]); and
(iii) growing a second layer (InGaN layer 18, Para [0029]) comprising III-V materials and having a thickness within an approximate range of 1-100nm (Para [ 0029], thereby reducing a surface roughness (InGaN layer 18, Para [ 0029]) compared to the final surface of the first layer (buffer layer 16, Para [ 0028]).
In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). "[A] prior art reference that discloses a range encompassing a somewhat narrower claimed range is sufficient to establish a prima facie case of obviousness." In re Peterson, 315 F.3d 1325, 1330, 65 USPQ2d 1379, 1382-83 (Fed. Cir. 2003). >See also In re Harris, 409 F.3d 1339, 74 USPQ2d 1951 (Fed. Cir. 2005).
But, Chua does not disclose explicitly a surface on a (111) crystal plane or on less than 5 degrees off of the (111) crystal plane; wherein the layer is grown leaving multiple thicker grown islands connected via thinner sections of the first layer and the thicker grown islands being grown with a gradient in their lattice constant providing a lattice constant of the first layer being different from the lattice of the final grown material, the difference in lattice constant between the first layer and the final grown material resulting in defect planes parallel to the (111) surface located below the grown islands, the defect planes providing strain relaxation of the final grown material.
In a similar field of endeavor, Vielemeyer discloses a surface on a (111) crystal plane or on less than 5 degrees off of the (111) crystal plane (Fig 10, Para [ 0071-0076]); wherein the layer is grown leaving multiple thicker grown islands connected via thinner sections of the first layer and the thicker grown islands being grown with a gradient in their lattice constant providing a lattice constant of the first layer being different from the lattice of the final grown material (Fig 10, Para [0030,0037, 0071-0076]), the difference in lattice constant between the first layer and the final grown material resulting in defect planes parallel to the (111) surface located below the grown islands, the defect planes providing strain relaxation of the final grown material (Fig 10, Para [ 0071-0076]) .
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Chua in light of Vielemeyer teaching “a surface on a (111) crystal plane or on less than 5 degrees off of the (111) crystal plane (Fig 10, Para [ 0071-0076]); wherein the layer is grown leaving multiple thicker grown islands connected via thinner sections of the first layer and the thicker grown islands being grown with a gradient in their lattice constant providing a lattice constant of the first layer being different from the lattice of the final grown material (Fig 10, Para [0030,0037, 0071-0076]), the difference in lattice constant between the first layer and the final grown material resulting in defect planes parallel to the (111) surface located below the grown islands, the defect planes providing strain relaxation of the final grown material (Fig 10, Para [ 0071-0076])” for further advantage such as substrate with crystal surface to ensures simplified and reliability of the semiconductor device and also reduces defects in epitaxially grown.
Regarding claim 28. Chua and Vielemeyer disclose the method of claim 19, Vielemeyer further discloses wherein steps (ii) and (iii) for growing the first layer and second layer are repeated one or more times, which thereby provides a gradual strain relaxation (Fig 10, Para [0071-0076]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Chua in light of Vielemeyer teaching “wherein steps (ii) and (iii) for growing the first layer and second layer are repeated one or more times, which thereby provides a gradual strain relaxation (Fig 10, Para [ 0071-0076])” for further advantage such as substrate with crystal surface to ensures simplified and reliability of the semiconductor device and also reduces defects in epitaxially grown.
Regarding claim 31. Chua and Vielemeyer disclose the method of claim 28, Chua further discloses wherein steps (i)-(iii) for manufacturing the semiconductor material are performed with group III and group V materials in heated solid form or melted form (Para [ 0026-0029], GAN is III-V material).
Regarding claim 34. Chua and Vielemeyer disclose the method of claim 31, Chua further discloses wherein the steps (i)-(iii) for manufacturing the semiconductor material are performed with a combination of the respective sources of the group III and group V materials (Para [0026-0029], GAN is III-V material).
Regarding claim 35. Chua and Vielemeyer disclose the method of claim 28, Chua further discloses wherein the steps (i)-(iii) for manufacturing the semiconductor material are performed in a Molecular Beam Epitaxy machine (Para [0026-0029], MBE process).
Regarding claim 36. Chua and Vielemeyer disclose the method of claim 28, Chua further discloses wherein the steps (i)-(iii) for manufacturing the semiconductor material are performed in an in-line horizontal deposition machine (Para [0026-0029], MBE process. It is evidence by Hussain US 74941887,” The deposition of the device layers 116 is typically performed in an epitaxial chamber such as a Metal-Organic Chemical Vapor Deposition (MOCVD) machine or a Molecular Beam Epitaxial (MBE) machine”, Col 10, lines 1-15).
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Chua et al (US 2009/0001416 A1; hereafter Chua) in view of Vielemeyer et al (US 2011/0049681 A1; hereafter Vielemeyer) as applied claims above and further in view of LIU et al (US 2019/0341524 A1; hereafter LIU).
Regarding claim 21. Chua and Vielemeyer disclose the method of claim 19, But Chua and Vielemeyer does not disclose explicitly wherein the first layer comprises AIA s1-zSbz and z is within a range of 0-1.0.
In a similar field of endeavor, LIU discloses wherein the first layer comprises AIA s1-zSbz and z is within a range of 0-1.0 (Para [0020]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Chua and Vielemeyer in light of LIU teaching “wherein the first layer comprises AIA s1-zSbz and z is within a range of 0-1.0 (Para [0020])” for further advantage such as reliable semiconductor layer formation with desire composition which enhance performance of the semiconductor device.
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Chua et al (US 2009/0001416 A1; hereafter Chua) in view of Vielemeyer et al (US 2011/0049681 A1; hereafter Vielemeyer) as applied claims above and further in view of Campbell et al (US 2017/0244002 A1; hereafter Campbell).
Regarding claim 22. Chua and Vielemeyer disclose the method of claim 19, But Chua and Vielemeyer does not disclose explicitly wherein the first layer comprises A1-ylnyAs1-zSbz, and y and z are each separately within a range of 0-1.0.
In a similar field of endeavor, Campbell discloses wherein the first layer comprises A1-ylnyAs1-zSbz, and y and z are each separately within a range of 0-1.0 (Para [0062]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Chua and Vielemeyer in light of Campbell teaching “wherein the first layer comprises A1-ylnyAs1-zSbz, and y and z are each separately within a range of 0-1.0 (Para [0062])” for further advantage such as reliable semiconductor layer formation with desire composition which enhance performance of the semiconductor device.
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Chua et al (US 2009/0001416 A1; hereafter Chua) in view of Vielemeyer et al (US 2011/0049681 A1; hereafter Vielemeyer) as applied claims above and further in view of Ergun et al (US 2015/0179844 A1; hereafter Ergun).
Regarding claim 24. Chua and Vielemeyer disclose the method of claim 19, But Chua and Vielemeyer does not disclose explicitly wherein the second layer comprises A11-xGaxAs1-zSbz, and x and z are each separately within a range of 0-1.0.
In a similar field of endeavor, Ergun discloses wherein the second layer comprises A11-xGaxAs1-zSbz, and x and z are each separately within a range of 0-1.0 (claim 5).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Chua and Vielemeyer in light of Ergun teaching “wherein the second layer comprises A11-xGaxAs1-zSbz, and x and z are each separately within a range of 0-1.0 (claim 5)” for further advantage such as reliable semiconductor layer formation with desire composition which enhance performance of the semiconductor device.
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Chua et al (US 2009/0001416 A1; hereafter Chua) in view of Vielemeyer et al (US 2011/0049681 A1; hereafter Vielemeyer) as applied claims above and further in view of FUJITA et al (US 2023/0134457 A1; hereafter FUJITA).
Regarding claim 25. Chua and Vielemeyer disclose the method of claim 19, But Chua and Vielemeyer does not disclose explicitly wherein the second layer comprises A11-x-yGaxlnyAs1-zSbz,the sum of x and y is less than or equal to 1, x and y are each greater than 0, and z is within a range of 0-1.0.
In a similar field of endeavor, FUJITA discloses wherein the second layer comprises A11-x-yGaxlnyAs1-zSbz,the sum of x and y is less than or equal to 1, x and y are each greater than 0, and z is within a range of 0-1.0 (Para [ 0062-0063, 0071-0072]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Chua and Vielemeyer in light of FUJITA teaching “wherein the second layer comprises A11-x-yGaxlnyAs1-zSbz,the sum of x and y is less than or equal to 1, x and y are each greater than 0, and z is within a range of 0-1.0 (Para [ 0062-0063, 0071-0072])” for further advantage such as reliable semiconductor layer formation with desire composition which enhance performance of the semiconductor device.
Claims 29-30 are rejected under 35 U.S.C. 103 as being unpatentable over Chua et al (US 2009/0001416 A1; hereafter Chua) in view of Vielemeyer et al (US 2011/0049681 A1; hereafter Vielemeyer) as applied claims above and further in view of Song et al (US 2009/0101888 A1; hereafter Song).
Regarding claim 29. Chua and Vielemeyer disclose the method of claim 19, But Chua and Vielemeyer does not disclose explicitly wherein steps (i)-(iii) for manufacturing the semiconductor material are performed under vacuum pressure less than 1 x 10-4 Torr.
In a similar field of endeavor, Song discloses wherein steps (i)-(iii) for manufacturing the semiconductor material are performed under vacuum pressure less than 1 x 10-4 Torr (Para [0043]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Chua and Vielemeyer in light of Song teaching “wherein steps (i)-(iii) for manufacturing the semiconductor material are performed under vacuum pressure less than 1 x 10-4 Torr (Para [ 0043])” for further advantage such as improved semiconductor structure.
Regarding claim 32. Chua and Vielemeyer in light of Song disclose the method of claim 29, Chua further disclose wherein the steps (i)-(iii) for manufacturing the semiconductor material are performed with heated solid or melted sources as the source of group III materials, and hydrides as the source of group V materials (Para [ 0026-0029], GAN is III-V material).
Claim 30 and 33 are rejected under 35 U.S.C. 103 as being unpatentable over Chua et al (US 2009/0001416 A1; hereafter Chua) in view of Vielemeyer et al (US 2011/0049681 A1; hereafter Vielemeyer) as applied claims above and further in view of NAKATA et al (US 2018/0204928 A1; hereafter NAKATA).
Regarding claim 30. Chua and Vielemeyer disclose the method of claim 19, But Chua and Vielemeyer does not disclose explicitly wherein steps (i)-(iii) for manufacturing the semiconductor material are performed under pressure greater than or equal to 1 x 10-4 Torr.
In a similar field of endeavor, NAKATA discloses wherein steps (i)-(iii) for manufacturing the semiconductor material are performed under pressure greater than or equal to 1 x 10-4 Torr (Para [0038-0042]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Chua and Vielemeyer in light of NAKATA teaching “wherein steps (i)-(iii) for manufacturing the semiconductor material are performed under pressure greater than or equal to 1 x 10-4 Torr (Para [0038-0042])” for further advantage such as improved semiconductor structure.
Regarding claim 33. Chua, Vielemeyer and NAKATA disclose the method of claim 30, Chua further disclose wherein the steps (i)-(iii) for manufacturing the semiconductor material are performed with a combination of the respective sources of the group III and group V materials (Para [ 0026-0029], GAN is III-V material).
Claim 38 is rejected under 35 U.S.C. 103 as being unpatentable over Chua et al (US 2009/0001416 A1; hereafter Chua) in view of Vielemeyer et al (US 2011/0049681 A1; hereafter Vielemeyer) as applied claims above and further in view of Tu et al (US 2019/0067516 A1; hereafter Tu).
Regarding claim 38. Chua and Vielemeyer disclose comprising a semiconductor material made by the method of claim 19. But Chua and Vielemeyer does not disclose explicitly a solar cell.
In a similar field of endeavor, Tu discloses a solar cell (Para [0003] discloses “semiconductor composed of III-V group elements, for example, GaP, GaAs, or GaN. A semiconductor device may be an optoelectronic semiconductor device such as a light emitting diode (LED), a laser or a solar cell, or a power device”).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Chua and Vielemeyer in light of Tu teaching “a solar cell (Para [0003] discloses “semiconductor composed of III-V group elements, for example, GaP, GaAs, or GaN. A semiconductor device may be an optoelectronic semiconductor device such as a light emitting diode (LED), a laser or a solar cell, or a power device”)” for further advantage such as improve reliability of optoelectronic devices by using well-known semiconductor materials.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOIN M RAHMAN whose telephone number is (571)272-5002. The examiner can normally be reached 8:30-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MOIN M RAHMAN/Primary Examiner, Art Unit 2898
Prosecution Insights