Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s amendments and remarks filed in response to the previous Non-Final Office Action have been fully considered and are persuasive with respect to the previously applied obviousness-type double patenting rejection.
The previous Office Action rejected claims 1, 3-4, 6, and 8 under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 1-4 and 6 of copending U.S. Application No. 18/712,704 in view of Hatanaka et al.
Independent claim 1 has been amended to recite, inter alia:
“an insulating protective layer provided on and entirely covering an inner wall of each of the plurality of perforated holes, wherein the insulating protective layer prevents the anodized film material of the body from being exposed at the inner wall of each of the plurality of perforated holes.”
The Examiner agrees that these amendments materially distinguish the presently claimed subject matter from the claims relied upon in copending U.S. Application No. 18/712,704.
In particular, claim 1 of copending U.S. Application No. 18/712,704 recites a metal layer provided on an inner wall of a perforated hole. The presently amended claim 1, however, affirmatively requires an insulating protective layer that entirely covers the inner wall of each of a plurality of perforated holes and prevents the anodized film material from being exposed at those inner walls. Thus, the amended claim does not merely require the presence of a layer on the perforated-hole wall, but requires a specific insulating layer having complete inner-wall coverage and a particular structural relationship with the underlying anodized film material.
The previous combination with Hatanaka et al. does not establish that the claims of copending U.S. Application No. 18/712,704 would have rendered obvious this newly claimed complete insulating coverage relationship. Accordingly, the Examiner agrees that amended claim 1 is patentably distinct from the claims relied upon in the previous obviousness-type double patenting rejection.
Claims 3, 4, 6, and 8 depend from amended claim 1 and therefore incorporate these newly added limitations.
With respect to amended claim 3, the claim additionally requires that “the insulating protective layer is in a parylene form.” The claims of copending U.S. Application No. 18/712,704 relied upon previously recite metal materials including titanium, copper, gold, and nickel. Such metallic materials do not constitute parylene. Accordingly, the prior characterization that parylene could be broadly interpreted as one of the recited metallic materials is no longer maintained.
With respect to amended claim 4, the claim requires “a metal layer is interposed between the inner wall of each of the perforated holes and the insulating protective layer.” The amended claim therefore requires a structural arrangement including the anodized-film inner wall, an intervening metal layer, and the insulating protective layer. The claims of copending U.S. Application No. 18/712,704 relied upon in the previous rejection do not establish this complete relationship together with the newly added limitations of amended claim 1.
Similarly, amended claim 6 requires that “the metal layer is interposed between the insulating protective layer and the inner wall of each of the perforated holes.” The previous double patenting rejection does not establish this claimed metal-layer/insulating-layer relationship together with complete inner-wall coverage by the insulating protective layer.
Amended claim 8 further requires that “the insulating protective layer entirely covers the micro-trenches provided on the inner wall of each of the plurality of perforated holes.” Although claim 3 of copending U.S. Application No. 18/712,704 recites a metal layer entirely covering fine trenches, a metal layer covering fine trenches does not establish the presently claimed insulating protective layer entirely covering such micro-trenches while also satisfying amended claim 1.
Accordingly, the previous obviousness-type double patenting rejection of claims 1, 3–4, 6, and 8 is withdrawn.
The withdrawal of the double patenting rejection, however, does not establish that the amended claims are patentable over the prior art. Applicant’s amendments distinguish the present claims from the claims of copending U.S. Application No. 18/712,704, but the newly added limitations are taught or suggested, in relevant part, by other prior art of record. In particular, Ahn et al. disclose an anodic oxide film sheet having through-holes and a thin protective film formed on the inner surface of each through-hole, including uniform thin-film deposition on inner-wall regions. Kimura et al. further disclose probe-card structures having electrically conductive probes inserted through a plurality of insulated through-holes and electrically connected with circuit-board structures.
Thus, Applicant’s arguments directed to the previously applied double patenting rejection are persuasive and render that rejection moot; however, the amendments do not overcome the separate prior-art issues discussed below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7 & 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamashita et al. (U.S. 2014/0085829 A1) in view of Ahn et al. (U.S. 2021/0251077 A1).
Regarding claim 1, Yamashita et al. disclose in Figs. 4-5 an anodized film structure, comprising: a body made of an anodized film material (anodized film 8 formed by anodizing aluminum substrate 7, see paragraph [0117]); and a plurality of perforated holes provided in the body (through-holes 9 formed in and extending through the anodized film 8, see paragraph [0117]).
Yamashita et al. are not understood to explicitly disclose an insulating protective layer provided on and entirely covering an inner wall of each of the plurality of perforated holes, wherein the insulating protective layer prevents the anodized film material of the body from being exposed at the inner wall of each of the plurality of perforated holes.
Ahn et al. disclose an insulating protective layer provided on and entirely covering an inner wall of each of the plurality of perforated holes, wherein the insulating protective layer prevents the anodized film material of the body from being exposed at the inner wall of each of the plurality of perforated holes (see Fig. 7, wherein an insulating protective layer provided on and entirely covering an inner wall of each of the plurality of perforated holes, wherein an anodic oxide film sheet 10 is provided with through-holes H and a first thin film layer 11 is formed on the inner surface H′ of each through-hole H, with the first thin film layer 11 being provided in the form of coating the inner surface H′ of the through-hole H to a predetermined thickness; see paragraph [0159]), wherein the first thin film layer 11 is an insulating layer because Ahn et al. disclose that the first thin film layer 11 may be formed of electrically insulating materials including aluminum oxide (Al₂O₃), yttrium oxide (Y₂O₃), aluminum nitride (AlN), silicon dioxide (SiO₂), and silicon nitride (Si₃N₄) (see paragraph [0064]). Accordingly, the coating of the inner surface H′ of each through-hole H with the insulating first thin film layer 11 results in the underlying anodic oxide film material being covered by the insulating protective layer rather than exposed at the coated inner wall).
It would have been obvious to one skilled in the art, prior to the effective filing date, to modify Yamashita et al. by incorporating an insulating protective layer provided on and entirely covering an inner wall of each of the plurality of perforated holes, wherein the insulating protective layer prevents the anodized film material of the body from being exposed at the inner wall of each of the plurality of perforated holes, as taught by Ahn et al., as doing so would protect the inner surfaces of the perforated holes against abrasion, corrosion, and chemical damage because Ahn et al. emphasize in paragraph [0167] that providing the first thin film layer on the inner surface of the through-hole provides chemical resistance and prevents corrosion or chemical reaction at the inner surface of the through-hole, thereby improving durability of the anodized film structure.
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Regarding claim 2, Yamashita et al. disclose the anodized film structure of claim 1 as discussed above.
Yamashita et al. are not understood to explicitly disclose that the insulating protective layer is provided on the inner wall of each of the perforated holes and a surface of the body, and that the insulating protective layer is evenly formed with a uniform thickness on the inner wall of each of the perforated holes and the surface of the body.
Ahn et al. disclose the insulating protective layer provided on both the surface of the anodic oxide film body and the inner surface of each through-hole (first thin film layer 11 provided on the upper and lower surfaces of anodic oxide film sheet 10 and on the inner surface H′ of each through-hole H, see paragraph [0171]). Ahn et al. further disclose that the first monoatomic layer is formed to the same thickness on the surface and inner-wall regions, satisfying T1=T2=T3 (see paragraph [0104]).
It would have been obvious to one skilled in the art, prior to the effective filing date, to modify Yamashita et al. by forming the insulating protective layer on both the surface of the anodized film body and the inner surfaces of the perforated holes with uniform thickness as taught by Ahn et al., as doing so would provide consistent and uniform protective coverage throughout the anodized film structure because Ahn et al. emphasize in paragraph [0104] that the monoatomic layer is formed to the same thickness on the surface and inner-wall regions.
Regarding claim 3, Yamashita et al. disclose the anodized film structure of claim 1 as discussed above.
Yamashita et al. are not understood to explicitly disclose that the insulating protective layer is in a parylene form.
Kimura et al. disclose electrically insulating films formed on respective inner walls of through-holes, wherein the electrically insulating films may be organic insulating materials such as polyimide or epoxy resin and conform to the inner shape of the through-holes (see paragraph [0026]).
It would have been obvious to one skilled in the art, prior to the effective filing date, to modify Yamashita et al. by employing a known conformal organic insulating coating material for the insulating protective layer as taught by Kimura et al., as doing so would electrically insulate the through-hole walls while providing a coating conforming to the inner shape of the through-holes because Kimura et al. emphasize in paragraph [0026] that electrically insulating organic films may be formed on the respective inner walls of the through-holes in a tubular shape conforming to the inner shape thereof.
Regarding claim 4, Yamashita et al. disclose the anodized film structure of claim 1 as discussed above and further disclose metal 10 provided within the through-holes 9 of the anodized film 8 (see paragraph [0117]).
Yamashita et al. are not understood to explicitly disclose the claimed arrangement wherein a metal layer is interposed between the inner wall of each perforated hole and the insulating protective layer.
Ahn et al. disclose an insulating protective thin film layer formed on and coating the inner surface of each through-hole to a predetermined thickness (see paragraph [0159]).
It would have been obvious to one skilled in the art, prior to the effective filing date, to modify the metal-containing through-hole structure of Yamashita et al. by applying the insulating protective thin film layer of Ahn et al. over the metal associated with the through-hole wall, thereby positioning the metal between the underlying inner wall and the insulating protective layer, as doing so would protect the underlying through-hole structure from abrasion, corrosion, and chemical damage because Ahn et al. emphasize in paragraph [0167] that providing the first thin film layer on the inner surface of the through-hole prevents corrosion or chemical reaction at the through-hole surface.
Regarding claim 5, Yamashita et al. disclose the anodized film structure of claim 1 as discussed above.
Yamashita et al. are not understood to explicitly disclose a plurality of the anodized film bodies stacked with a bonding layer provided between each of the bodies.
Ahn et al. disclose a plurality of anodic oxide film structures provided together to form a multilayer wiring board (see paragraph [0141]).
It would have been obvious to one skilled in the art, prior to the effective filing date, to modify Yamashita et al. by providing a plurality of the anodized film bodies in a stacked multilayer configuration with bonding between adjacent bodies as taught by Ahn et al., as doing so would provide a mechanically integrated multilayer structure having improved dimensional stability and durability because Ahn et al. emphasize in paragraph [0143] that the resulting multilayer wiring board reduces warping and improves durability of the product.
Regarding claim 6, Yamashita et al. disclose the anodized film structure of claim 1 as discussed above and further disclose a heat conducting layer disposed on at least one surface of the anisotropically conductive anodized member and conductive metal associated with the through-holes (see paragraph [0025]).
Yamashita et al. are not understood to explicitly disclose the claimed arrangement wherein the metal layer is interposed between the insulating protective layer and the inner wall of each of the perforated holes.
Ahn et al. disclose an insulating protective thin film layer coating the inner surface of each through-hole to a predetermined thickness (see paragraph [0159]).
It would have been obvious to one skilled in the art, prior to the effective filing date, to modify the metal-containing anodized film structure of Yamashita et al. by applying the insulating protective thin film layer of Ahn et al. over the metal associated with the inner wall of each perforated hole, thereby positioning the metal layer between the inner wall and the insulating protective layer, as doing so would protect the underlying through-hole structure from abrasion and chemical degradation because Ahn et al. emphasize in paragraph [0167] that the thin film layer provided on the inner surface of the through-hole prevents corrosion or chemical reaction at the through-hole surface.
Regarding claim 7, Yamashita et al. disclose the anodized film structure of claim 6 as discussed above and further disclose a plurality of perforated through-holes in the anodized film structure (see paragraph [0117]).
Yamashita et al. are not understood to explicitly disclose that, in at least some of the plurality of perforated holes, the insulating protective layer covers the metal layer so that the metal layer is not exposed, while in the remaining perforated holes the metal layer is exposed.
Kimura et al. disclose a plurality of through-holes having metal layers associated with the through-hole walls and conductive probes received through the through-holes and contacting the exposed metal layers (see paragraph [0039]).
It would have been obvious to one skilled in the art, prior to the effective filing date, to selectively expose the metal layer in through-holes requiring electrical contact while maintaining insulating protective coverage over metal in through-holes not requiring such contact, as doing so would permit electrical connection only at selected through-hole locations while maintaining insulation at other locations because Kimura et al. emphasize in paragraph [0039] that the probe ends contact the metal layers within the through-holes to establish the required electrical connection.
Regarding claim 9, Ahn et al. disclose an anodized film structure comprising a body made of an anodized film material (anodic oxide film sheet 10 formed by anodizing an aluminum substrate, see paragraph [0037]); a plurality of perforated holes provided in the body (through-holes H provided in the anodic oxide film sheet 10, see paragraph [0156]); and an insulating protective layer provided on and entirely covering an inner wall of each of the plurality of perforated holes (first thin film layer 11 coating the inner surface H′ of each through-hole H to a predetermined thickness, see paragraph [0159]). Ahn et al. further disclose use of the anodic oxide film structure in a probe card wherein a probe is provided in a through-hole (see paragraph [0161]).
Ahn et al. are not understood to explicitly disclose an inspection device comprising electrically conductive contact pins inserted into the plurality of perforated holes and a circuit unit connected to the electrically conductive contact pins in the complete arrangement recited by claim 9.
Kimura et al. disclose electrically conductive contact pins inserted into the plurality of perforated holes (probes 200 having first and second ends received through associated through-holes of guide plates 100a and 100b, see paragraph [0039]) and a circuit unit connected to the electrically conductive contact pins (main circuit board 700 comprising a printed circuit board having electrodes interconnected by conductive lines, see paragraph [0033]).
It would have been obvious to one skilled in the art, prior to the effective filing date, to modify the anodic oxide film structure of Ahn et al. by incorporating the electrically conductive probes and connected circuit-board arrangement taught by Kimura et al., as doing so would provide an inspection device capable of electrically testing a semiconductor wafer or semiconductor device while utilizing the protective coated through-holes of Ahn et al. because Kimura et al. emphasize in paragraph [0040] that the probes contact electrodes of the measuring object and thereby enable the tester to measure electrical characteristics of the measuring object.
Allowable Subject Matter
Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
In terms of claim 8, the prior art of record does not teach alone or in combination of “wherein the inner wall of each of the plurality of perforated holes is provided with micro-trenches defined by peaks and valleys repeatedly arranged in a circumferential direction of each of the plurality of perforated and wherein the insulating protective layer entirely covers the micro-trenches provided on the inner wall of each of the plurality of perforated holes” in combination with all other elements in claim 1.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled "Comments on Statement of Reasons for Allowance."
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. 2010/0032830 A1 to Chang et al. disclose a three-dimensional conducting structure comprises a substrate, a first redistributed conductor, a second redistributed conductor and an insulator. The substrate has an active surface, a passive surface opposite to the active one, a pad on the active surface and a through hole. The first redistributed conductor comprises a projecting portion and a receiving portion. The projecting portion is projected from the active surface and electrically connected to the pad. The receiving portion is outside the active surface and in contact with the projecting portion, both of which constitute a recess communicating with the through hole. The second redistributed conductor is positioned within the through hole and the recess, in contact with the receiving portion, and extended toward the passive surface along the through hole. The insulator is filled between the second redistributed conductor and the substrate and between the second redistributed conductor and the projecting portion.
U.S. 2005/0012217 A1 to Mori et al. disclose a multilayer wiring board comprising a core board, and a wiring layer and an electrically insulating layer that are stacked on one surface of said core board, a thermal expansion coefficient of said core board in XY directions falls within a range of 2 to 20 ppm, a core member for said core board is a core member selected from silicon, ceramics, glass, a glass-epoxy composite, and metal, said core board is provided with a plurality of through holes that are made conductive between the front and the back by a conductive material, and a capacitor is provided on one surface of said core board, wherein said capacitor comprises an upper electrode being the conductive material in said through hole, and a lower electrode disposed so as to confront said upper electrode via a dielectric layer.
U.S. 2021/0074685 A1 to Chang discloses a memory device, a semiconductor device and their manufacturing methods are provided. One of the methods may include: providing a first die and a plurality of second dies, the first die having a first pad, each of the plurality of second dies having a second pad; stacking the plurality of second dies on the first die, the second pads and the first pad arranged in a stepwise manner, and projections of the second pads of any two adjacent second dies on the first die partially overlapped; forming a connecting hole passing through the second dies; and forming a conductive body filling the connecting hole and connecting the first pad and the second pads. This method simplifies the manufacturing process of a semiconductor device, reduces the cost thereof, and improves the production yield.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRUNG NGUYEN whose telephone number is (571)272-1966. The examiner can normally be reached on Mon- Friday 8AM - 4:00PM Eastern Time. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Huy Phan can be reached on 571-272-7924. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
Examiner: /Trung Q. Nguyen/- Art 2858
/HUY Q PHAN/ Supervisory Patent Examiner, Art Unit 2858
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