Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings submitted on 11/20/2025 have been considered and entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
As per claims 1, 13, and 20, the claims recite “receive executable files comprising different code, for executing a parallel computing.” It is unclear what the claimed code must be different from. The claims do not state whether the code in each executable file is different from the code in the other executable files, different from code previously stored in the slave microcontrollers, different for each respective slave microcontroller, or different merely in version, format, functionality, or content. The claims do not require that respective executable files containing respective different code be distributed to respective slave microcontrollers. Consequent, the scope of “different code” cannot be determined with reasonable certainty.
Claims 2-12 and 14-19 are rejected under 35 U.S.C. § 112(b) as being indefinite because they depend from rejected independent claims.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Graif et al. US PG-Pub 2020/0089632 in view of Raker et al. US PG-Pub 2006/0294290 (hereinafter Raker).
As per claim 1, Graif teaches a computing apparatus, comprising:
a plurality of microcontrollers, including a master microcontroller and at least two slave microcontrollers (Fig. 2, and para. 0040 describes device 202 as a master and multiple slave devices; each includes processing circuits (microcontrollers) such as processors, control logics, and transceivers);
a bus, operatively interconnecting the plurality of microcontrollers (para. 0042 describes serial bus 220 interconnecting master 202 and multiple slaves 222s);
an input/output (I/O) interface operatively interconnected to the master microcontroller (para. 0040 discloses interface controller 204 for managing access to the serial bus and communications – this serves as the I/O interface); and
a power supply (para. 0038 describes the processing circuit including power management functions to operate the apparatus, inherently requiring a power supply);
wherein the master microcontroller is operative to:
receive a response from the at least two slave microcontrollers (para. 0056-0059 and 0071 describe slaves sending responses/interrupt requests to the master over the bus, and master detecting/receiving them); and
transmit an aggregated response through the I/O interface (para. 0081 describes master processing responses from the slaves (including pulse counts, identifiers, actions) and communicating results through its interface controller 204 which is equivalent to the aggregated response).
Graif teaches receiving data through the interface controller but did not specifically indicate that the data are executable files. However, the secondary reference Raker teaches receives executable files through an interface (Fig. 3 and paragraph 0020-0024 where the master receives new program code files (firmware/executable for in-application programming), for the purpose of improving efficiency and reducing downtime when distributing programming or executable codes to multiple devices.
Graif teaches distribute the data to the at least two slave microcontrollers (para. 0040-0043 and Fig. 2 show master 202 communicating over 220 to the multiple slaves 222s; the executable or programmable codes are taught by the secondary reference Raker);
It would have been obvious to one of ordinary skill in the art at, before the effective filing date of the claimed invention, to incorporate the teaching of Raker of having executable codes into the teaching of Graif to be able to efficiently distribute the codes to multiple devices which reduces downtime and improves communication among master-slave devices and yield predictable results.
Regarding the newly added limitation that executable files comprise different code for executing a parallel computation, Raker teaches that each programmable device may be programmed with its own firmware and that the master determines which programmable devices are to be programmed and with the new program-code file each programmable device is to be programmed. See Raker, paragraphs [0003] and [0021]. Raker further teaches that each available program-code file includes information identifying the PWBA or device to which the file is applicable, together with file version and revision information, and that the master stores a plurality of program-code files. See Raker, paragraphs [0022] and [0041]. Thus, Raker teaches executable files containing different device-specific code.
Graif further teaches a master device connected to a plurality of slave devices having respective processing circuits, wherein the slave devices may perform different functions, including signal processing, display control, camera operation, sensor control, and other device-specific functions. See Graif, paragraphs [0039]-[0041]. It would have been obvious to one of ordinary skill in the art to use Raker’s device-specific executable files in Graif’s heterogeneous master-slave processing system so that the respective slave processors receive and execute code corresponding to their respective functions.
It would have been obvious to one of ordinary skill in the art at, before the effective filing date of the claimed invention, to recognize that execution of the respective device-specific code by the plurality of slave processor concurrently constitutes execution of a parallel computation under the broadest reasonable interpretation of the claim. The modification would have been predictably allowed Graif’s multiple slave processors to perform their respective processing tasks while retaining Raker’s stated advantages of reduced programming time, reduced system downtime, and efficient programming of multiple programming devices.
As per claim 2, Graif teaches the computing apparatus of claim 1, wherein the bus operatively interconnects the plurality of microcontrollers in parallel (See Fig. 2, wherein element 220 interconnects the microcontrollers in parallel).
As per claim 3, Graif teaches the computing apparatus of claim 1, wherein the bus is composed of hard wires (para. 0042-0043, I2C or I3C are hard wires).
As per claim 4, the combination of Graif in view of Raker teaches the computing apparatus of claim 2, wherein the bus is composed of two hard wires, one for serial data (SDA) signal and one for serial clock (SCL) signal (Graif Fig. 3 or 4, SDA and SCL).
As per claim 5, the combination of Graif in view of Raker teaches the computing apparatus of claim 4, wherein the master microcontroller distributes the executable files and receives a response from the at least two slave microcontrollers using an inter-integrated circuit (I2C) communication protocol (Graif para. 0042 teaches a serial bus connecting the master and slave devices, which can be implemented using standard protocols such as I2C. Raker 0017 explicitly mention using I2C as an implementation for master-slave communication to send executable files and receives responses. It would have been obvious to use I2C in Graif’s system because Raker teaches it as a known and common choice for master-slave microcontroller communications, yielding predictable results.
As per claim 6, the combination of Graif in view of Raker teaches the computing apparatus of claim 1, wherein the master microcontroller receives the executable files and transmits the aggregated response through the I/O interface using the universal asynchronous receiver-transmitter (UART) protocol (Graif para. 0040 teaches an I/O interface for sending and receiving data. Raker teaches the programming code or executable files). Using UART is a known equivalent to other serial communication interfaces for such data exchange; substituting UART for other protocols in Graif’s interface would have been an obvious design choice as Graif already shows serial protocols (para. 0042-0043, I2C or I3C)).
As per claim 7, the combination of Graif in view of Raker teaches the computing apparatus of claim 1, wherein each of the executable files received through the I/O interface comprise specific instructions, to be executed by each of the plurality of microcontrollers (Raker para. 0039, ‘program instructions), for executing a parallel computation (As shown from Graif, Fig. 2, and Raker Fig. 4, the execution is done in parallel among slave devices).
As per claim 8, the combination of Graif in view of Raker teaches the computing apparatus of claim 7, wherein the executable files are compiled on a computer connected to the master node and are received through the I/O interface (Graif para. 0040 and Raker para. 0039, wherein a computer host compiled the code and sends them via the I/O interface).
As per claim 9, the combination of Graif in view of Raker teaches the computing apparatus of claim 1, wherein the master microcontroller is further operative to send a command to the at least two slave microcontrollers, to set the at least two slave microcontrollers in programming mode (Graif Fig. 2, the master device 202 sends commands to slave devices such as Slave 1 and Slave 2; see also Fig. 3 and para. 0020 of Raker).
As per claim 10, the combination of Graif in view of Raker teaches the computing apparatus of claim 9, wherein, when in programming mode, each of the at least two slave microcontrollers is operative to:
write the executable file on the slave microcontroller flash memory; restart itself; and wait in idle mode (see Raker Fig. 3 and para. 0022-0036 wherein the program file is saved on a flash memory, can restart or reboot and wait in an idle or sleep mode).
As per claim 11, the combination of Graif in view of Raker teaches the computing apparatus of claim 10, wherein the master microcontroller is further operative to send a command to the at least two slave microcontrollers, to run the executable files (Graif Fig. 2, the master device 202 sends commands to slave devices such as Slave 1 and Slave 2; See also Raker, para. 0019 and 0028 for executable code).
As per claim 12, the combination of Graif in view of Raker teaches the computing apparatus of claim 11, wherein the master microcontroller is further operative to send a command to the at least two slave microcontrollers (Graif Fig. 2, the master device 202 sends commands to slave devices such as Slave 1 and Slave 2), to send a response to the master microcontroller (Graif para. 0070 and 0071, response to the master controller).
As per claim 13, the process of claim 13 is performed by the computing apparatus of claim 1, thus are rejected for the same reasons.
As per claim 14, it’s rejected for the same reasons set forth above in claim 8.
As per claim 15, it’s rejected for the same reasons set forth above in claim 9.
As per claim 16, it’s rejected for the same reasons set forth above in claim 10.
As per claim 17, it’s rejected for the same reasons set forth above in claim 11.
As per claim 18, it’s rejected for the same reasons set forth above in claim 12.
As per claim 19, it’s rejected for the same reasons set forth above in claim 8.
As per claim 20, it’s rejected for the same reasons as set forth above in claim 1.
Response to Arguments
Applicant's arguments filed 11/20/2025 have been fully considered but they are not persuasive. Applicant argues that Graif and Raker fail to teach executable files comprising different code for executing a parallel computation. The argument is not persuasive.
Raker is not limited to a single executable file applicable to every programmable device. Raker expressly determines, based on device identification and firmware version information, which new program-code file is applicable to each programmable device (paragraphs [0019]-[0022]). Raker also stores plural program-code files having respective device-identification and version information. Accordingly, Raker teaches or at least suggests that different programmable devices will receive different device-specific program code.
Graif teaches a plurality of slave processors capable of performing different device functions when Raker’s device specific programming technique is applied to Graif’s heterogeneous slave processors, each slave processor receives executable code corresponding to its assigned function. The resulting processors are capable of concurrently executing their respective code, thereby performing a parallel computation as broadly claimed.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US Patent 7,792,904 teaches sharing material in a master-slave configuration.
US PG-Pub 2008/0320279 teaches a master device for managing a communications link to slave devices.
US PG-Pub 2008/0235493 teaches instruction communication techniques for multi-processor system including master and slave processors.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/IDRISS N ALROBAYE/Supervisory Patent Examiner, Art Unit 2181
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