DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 9/10/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The abstract and title are consistent with the requirements set forth in the MPEP 608.01(b) and 606, respectively.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 19 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 19 recites the limitations "the PCB aperture” and “the transmission lines" in lines 6 and 12, respectively. There is insufficient antecedent basis for these limitations in the claim because there is no previous mention of “a PCB aperture” and “transmission lines” in claims 19 and claim 1 which claim 19 is dependent on. For examination purposes and for proper antecedent basis, the limitations are being interpreted as "a PCB aperture” and “transmission lines" or “a plurality of transmission lines,” respectively. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Kikuchi et al. US PGPub. 2023/0345844 in view of Scheer et al. US PGPub. 2021/0342729. Regarding claim 1, Kikuchi teaches a packaging arrangement (1, fig. 1 and 6-7) [0029] for a quantum processor chip (10, fig. 1)[0030], arranged to be cooled by being placed in a cryostat (30, fig. 1) [0046], the packaging arrangement (1) comprising an attachment plate (bottom portion of 30, fig. 1; hereinafter called 30B) of a conductive material [0046], wherein the attachment plate (30B) is arranged to receive a board (substrate 15, fig. 1) [0030] in a stacked configuration where the board/substrate (15) faces a first (top) surface of the attachment plate (30B), the attachment plate (30B) comprising an attachment plate cavity (31, fig. 1) [0047]) on the first (top) surface, and comprising a ridge (33, fig. 6-7) [0061] arranged at least partly surrounding the attachment plate cavity (31) and arranged protruding from the first (top) surface, wherein the ridge (33) is arranged to receive the quantum processor chip (10) (Kikuchi et al., fig. 1 and 6-7). But Kikuchi fails to teach wherein the substrate (15) is a PCB. However, Scheer teaches a quantum packaging (fig. 3A) [0043] comprising a substrate (302, fig. 3A) [0043], wherein the substrate (302) is a printed circuit board (PCB) [0126] (Scheer et al., fig. 3A, [0126]). At the time before the effective filing of the claimed invention, it would have been obvious to one of ordinary skill in the art to make the simple substitute of the substrate of Kikuchi with the PCB of Scheer to enable signal lines communicate signals between the quantum chip and external control systems (Scheer et al., [0126]) as is well known in the art and such substitution is art recognized equivalence for the same purpose to obtain predictable results (see MPEP 2144.06). Regarding claim 2, Kikuchi in view of Scheer teaches the packaging arrangement (1) according to claim 1, wherein the ridge (33) comprises one or more openings (spacing in between ridges 33, see fig. 6 and 7; hereinafter called 33S) for receiving an adhesive (BL, fig. 4) [0058] for attaching the quantum processor chip (10) to the PCB attachment plate (30B) (Kikuchi et al., fig. 6-7). Regarding claim 4, Kikuchi in view of Scheer teaches the packaging arrangement (1) according to claim 1, wherein the ridge (33) forms a rectangular shape comprising four sections (33-top-left, 33-top-right, 33-bottom-left, 33-bottom-right; fig. 6-7) extending along respective four sides of the rectangular shape (Kikuchi et al., fig. 7). Regarding claim 18, Kikuchi in view of Scheer teaches a set (fig. 1) comprising the packaging arrangement (1) according to claim 1 and the quantum processor chip (10) (Kikuchi et al., fig. 1).
Allowable Subject Matter
Claims 3 and 5-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior arts of record taken alone or in combination neither anticipates nor renders obvious a packaging arrangement wherein “the first surface of the PCB attachment plate (120) comprises one or more attachment points (124) for receiving an adhesive for attaching the PCB (110) to the PCB attachment plate (120), wherein the respective attachment points are at least partly surrounded by a trench (125) in the PCB attachment plate (120)” as recited in claim 3 in combination with the rest of the limitations of claim 1; a packaging arrangement (100) wherein “two adjacent sections (122a, 122b) have a first width and other two sections (122c,122d) have a second width, wherein the widths are in a dimension along the first surface of the PCB attachment plate (120) and along a direction perpendicular to the respective extension directions of the sections, wherein the first width is larger than the second width” as recited in claim 5 in combination with the rest of the limitations are recited in claims 1 and 4; a packaging arrangement (100) comprising the PCB (110), where the PCB is arranged stacked with the PCB attachment plate (120), “the PCB (110) comprising an aperture (111) for receiving the quantum processor chip (101), and comprising a plurality of transmission lines (112) where respective first ends (113) of the transmission lines are arranged to be connected to the quantum processor chip and corresponding second ends (114) are arranged to be connected to respective cables, where the first and the second ends are arranged on a first surface of the PCB facing away from the of the PCB attachment plate (120), and wherein the PCB aperture (111) is arranged to surround the ridge (122) of the PCB attachment plate (120)” as recited in claim 6 in combination with the rest of the limitations of claim 1; and a packaging arrangement (100) comprising “a receiver arrangement (140) comprising a first receiver plate (141), where the PCB (110) and the PCB attachment plate (120) are arranged stacked with the receiver arrangement with the first surface of the PCB facing the first receiver plate (141), the first receiver plate comprising a plurality of through holes (143) for receiving respective cables for connecting to respective second ends (114) of the transmission lines (112) of the PCB (110), wherein the through holes (143) are arranged facing respective second ends (114) of the transmission lines (112)” as recited in claim 12 in combination with the rest of the limitations of claim 1. Claims 7-11 and 13-17 are also objected to as allowable for further limiting and depending upon allowable claims 6 and 12. Claim 19 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior arts of record taken alone or in combination neither anticipates nor renders obvious a method for assembling a quantum processor chip (101) to a packaging arrangement (100) comprising “pressing (S2) the PCB (110) to the PCB attachment plate (120), wherein the PCB aperture (111) is aligned with the ridge (122), and curing the first adhesive; applying (S3) a second adhesive to the ridge (122) and arranging the quantum processor chip (101) on the ridge; pressing (S4) the quantum processor chip (101) to the ridge (122) and curing the second adhesive; and arranging (S5) wire bonds between respective first ends (113) of the transmission lines (112) of the PCB (110) and respective pads arranged on the quantum processor chip (101)” as recited in claim 19 in combination with the rest of the limitations of claim 1.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kikuchi et al. US PGPub. 2021/0399196 also teaches a packaging arrangement (1, fig. 1) comprising a quantum processing chip arranged in an attachment plate cavity.
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/NDUKA E OJEH/Primary Examiner, Art Unit 2892
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